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#define PIN_CFG_FILCLKSEL BIT(12)
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#define PIN_CFG_IOLH_C BIT(13)
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#define PIN_CFG_SOFT_PS BIT(14)
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+ #define PIN_CFG_OEN BIT(15)
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#define RZG2L_MPXED_COMMON_PIN_FUNCS (group ) \
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(PIN_CFG_IOLH_##group | \
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#define SD_CH (off , ch ) ((off) + (ch) * 4)
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#define ETH_POC (off , ch ) ((off) + (ch) * 4)
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#define QSPI (0x3008)
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+ #define ETH_MODE (0x3018)
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#define PVDD_2500 2 /* I/O domain voltage 2.5V */
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#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
@@ -170,6 +172,8 @@ enum rzg2l_iolh_index {
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* @iolh_groupb_oi: IOLH group B output impedance specific values
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* @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported)
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* @func_base: base number for port function (see register PFC)
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+ * @oen_max_pin: the maximum pin number supporting output enable
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+ * @oen_max_port: the maximum port number supporting output enable
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*/
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struct rzg2l_hwcfg {
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const struct rzg2l_register_offsets regs ;
@@ -179,6 +183,8 @@ struct rzg2l_hwcfg {
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u16 iolh_groupb_oi [4 ];
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bool drive_strength_ua ;
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u8 func_base ;
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+ u8 oen_max_pin ;
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+ u8 oen_max_port ;
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};
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struct rzg2l_dedicated_configs {
@@ -782,6 +788,66 @@ static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps,
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return false;
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}
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+ static bool rzg2l_oen_is_supported (u32 caps , u8 pin , u8 max_pin )
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+ {
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+ if (!(caps & PIN_CFG_OEN ))
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+ return false;
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+
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+ if (pin > max_pin )
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+ return false;
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+
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+ return true;
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+ }
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+
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+ static u8 rzg2l_pin_to_oen_bit (u32 offset , u8 pin , u8 max_port )
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+ {
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+ if (pin )
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+ pin *= 2 ;
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+
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+ if (offset / RZG2L_PINS_PER_PORT == max_port )
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+ pin += 1 ;
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+
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+ return pin ;
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+ }
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+
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+ static u32 rzg2l_read_oen (struct rzg2l_pinctrl * pctrl , u32 caps , u32 offset , u8 pin )
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+ {
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+ u8 max_port = pctrl -> data -> hwcfg -> oen_max_port ;
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+ u8 max_pin = pctrl -> data -> hwcfg -> oen_max_pin ;
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+ u8 bit ;
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+
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+ if (!rzg2l_oen_is_supported (caps , pin , max_pin ))
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+ return 0 ;
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+
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+ bit = rzg2l_pin_to_oen_bit (offset , pin , max_port );
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+
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+ return !(readb (pctrl -> base + ETH_MODE ) & BIT (bit ));
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+ }
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+
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+ static int rzg2l_write_oen (struct rzg2l_pinctrl * pctrl , u32 caps , u32 offset , u8 pin , u8 oen )
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+ {
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+ u8 max_port = pctrl -> data -> hwcfg -> oen_max_port ;
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+ u8 max_pin = pctrl -> data -> hwcfg -> oen_max_pin ;
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+ unsigned long flags ;
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+ u8 val , bit ;
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+
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+ if (!rzg2l_oen_is_supported (caps , pin , max_pin ))
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+ return - EINVAL ;
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+
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+ bit = rzg2l_pin_to_oen_bit (offset , pin , max_port );
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+
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+ spin_lock_irqsave (& pctrl -> lock , flags );
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+ val = readb (pctrl -> base + ETH_MODE );
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+ if (oen )
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+ val &= ~BIT (bit );
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+ else
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+ val |= BIT (bit );
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+ writeb (val , pctrl -> base + ETH_MODE );
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+ spin_unlock_irqrestore (& pctrl -> lock , flags );
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+
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+ return 0 ;
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+ }
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+
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static int rzg2l_pinctrl_pinconf_get (struct pinctrl_dev * pctldev ,
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unsigned int _pin ,
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unsigned long * config )
@@ -819,6 +885,12 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
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return - EINVAL ;
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break ;
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+ case PIN_CONFIG_OUTPUT_ENABLE :
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+ arg = rzg2l_read_oen (pctrl , cfg , _pin , bit );
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+ if (!arg )
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+ return - EINVAL ;
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+ break ;
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+
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case PIN_CONFIG_POWER_SOURCE :
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ret = rzg2l_get_power_source (pctrl , _pin , cfg );
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if (ret < 0 )
@@ -920,6 +992,13 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
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rzg2l_rmw_pin_config (pctrl , IEN (off ), bit , IEN_MASK , !!arg );
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break ;
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+ case PIN_CONFIG_OUTPUT_ENABLE :
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+ arg = pinconf_to_config_argument (_configs [i ]);
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+ ret = rzg2l_write_oen (pctrl , cfg , _pin , bit , !!arg );
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+ if (ret )
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+ return ret ;
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+ break ;
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+
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case PIN_CONFIG_POWER_SOURCE :
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settings .power_source = pinconf_to_config_argument (_configs [i ]);
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break ;
@@ -1364,7 +1443,8 @@ static const u32 r9a07g043_gpio_configs[] = {
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static const u32 r9a08g045_gpio_configs [] = {
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RZG2L_GPIO_PORT_PACK (4 , 0x20 , RZG3S_MPXED_PIN_FUNCS (A )), /* P0 */
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RZG2L_GPIO_PORT_PACK (5 , 0x30 , RZG2L_MPXED_ETH_PIN_FUNCS (PIN_CFG_IOLH_C |
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- PIN_CFG_IO_VMC_ETH0 )), /* P1 */
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+ PIN_CFG_IO_VMC_ETH0 )) |
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+ PIN_CFG_OEN , /* P1 */
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RZG2L_GPIO_PORT_PACK (4 , 0x31 , RZG2L_MPXED_ETH_PIN_FUNCS (PIN_CFG_IOLH_C |
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PIN_CFG_IO_VMC_ETH0 )), /* P2 */
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RZG2L_GPIO_PORT_PACK (4 , 0x32 , RZG2L_MPXED_ETH_PIN_FUNCS (PIN_CFG_IOLH_C |
@@ -1374,7 +1454,8 @@ static const u32 r9a08g045_gpio_configs[] = {
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RZG2L_GPIO_PORT_PACK (5 , 0x21 , RZG3S_MPXED_PIN_FUNCS (A )), /* P5 */
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RZG2L_GPIO_PORT_PACK (5 , 0x22 , RZG3S_MPXED_PIN_FUNCS (A )), /* P6 */
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RZG2L_GPIO_PORT_PACK (5 , 0x34 , RZG2L_MPXED_ETH_PIN_FUNCS (PIN_CFG_IOLH_C |
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- PIN_CFG_IO_VMC_ETH1 )), /* P7 */
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+ PIN_CFG_IO_VMC_ETH1 )) |
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+ PIN_CFG_OEN , /* P7 */
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RZG2L_GPIO_PORT_PACK (5 , 0x35 , RZG2L_MPXED_ETH_PIN_FUNCS (PIN_CFG_IOLH_C |
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PIN_CFG_IO_VMC_ETH1 )), /* P8 */
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RZG2L_GPIO_PORT_PACK (4 , 0x36 , RZG2L_MPXED_ETH_PIN_FUNCS (PIN_CFG_IOLH_C |
@@ -1956,6 +2037,8 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = {
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},
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.drive_strength_ua = true,
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.func_base = 1 ,
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+ .oen_max_pin = 1 , /* Pin 1 of P0 and P7 is the maximum OEN pin. */
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+ .oen_max_port = 7 , /* P7_1 is the maximum OEN port. */
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};
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static struct rzg2l_pinctrl_data r9a07g043_data = {
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