29
29
#include "amdgpu_vm.h"
30
30
#include "amdgpu_amdkfd.h"
31
31
#include "amdgpu_dma_buf.h"
32
+ #include <uapi/linux/kfd_ioctl.h>
32
33
33
34
/* BO flag to indicate a KFD userptr BO */
34
35
#define AMDGPU_AMDKFD_USERPTR_BO (1ULL << 63)
@@ -400,18 +401,18 @@ static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
400
401
static uint64_t get_pte_flags (struct amdgpu_device * adev , struct kgd_mem * mem )
401
402
{
402
403
struct amdgpu_device * bo_adev = amdgpu_ttm_adev (mem -> bo -> tbo .bdev );
403
- bool coherent = mem -> alloc_flags & ALLOC_MEM_FLAGS_COHERENT ;
404
+ bool coherent = mem -> alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT ;
404
405
uint32_t mapping_flags ;
405
406
406
407
mapping_flags = AMDGPU_VM_PAGE_READABLE ;
407
- if (mem -> alloc_flags & ALLOC_MEM_FLAGS_WRITABLE )
408
+ if (mem -> alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE )
408
409
mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE ;
409
- if (mem -> alloc_flags & ALLOC_MEM_FLAGS_EXECUTABLE )
410
+ if (mem -> alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE )
410
411
mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE ;
411
412
412
413
switch (adev -> asic_type ) {
413
414
case CHIP_ARCTURUS :
414
- if (mem -> alloc_flags & ALLOC_MEM_FLAGS_VRAM ) {
415
+ if (mem -> alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM ) {
415
416
if (bo_adev == adev )
416
417
mapping_flags |= coherent ?
417
418
AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW ;
@@ -1160,24 +1161,24 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1160
1161
/*
1161
1162
* Check on which domain to allocate BO
1162
1163
*/
1163
- if (flags & ALLOC_MEM_FLAGS_VRAM ) {
1164
+ if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM ) {
1164
1165
domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM ;
1165
1166
alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE ;
1166
- alloc_flags |= (flags & ALLOC_MEM_FLAGS_PUBLIC ) ?
1167
+ alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC ) ?
1167
1168
AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED :
1168
1169
AMDGPU_GEM_CREATE_NO_CPU_ACCESS ;
1169
- } else if (flags & ALLOC_MEM_FLAGS_GTT ) {
1170
+ } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT ) {
1170
1171
domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT ;
1171
1172
alloc_flags = 0 ;
1172
- } else if (flags & ALLOC_MEM_FLAGS_USERPTR ) {
1173
+ } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR ) {
1173
1174
domain = AMDGPU_GEM_DOMAIN_GTT ;
1174
1175
alloc_domain = AMDGPU_GEM_DOMAIN_CPU ;
1175
1176
alloc_flags = 0 ;
1176
1177
if (!offset || !* offset )
1177
1178
return - EINVAL ;
1178
1179
user_addr = untagged_addr (* offset );
1179
- } else if (flags & (ALLOC_MEM_FLAGS_DOORBELL |
1180
- ALLOC_MEM_FLAGS_MMIO_REMAP )) {
1180
+ } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1181
+ KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP )) {
1181
1182
domain = AMDGPU_GEM_DOMAIN_GTT ;
1182
1183
alloc_domain = AMDGPU_GEM_DOMAIN_CPU ;
1183
1184
bo_type = ttm_bo_type_sg ;
@@ -1198,7 +1199,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1198
1199
}
1199
1200
INIT_LIST_HEAD (& (* mem )-> bo_va_list );
1200
1201
mutex_init (& (* mem )-> lock );
1201
- (* mem )-> aql_queue = !!(flags & ALLOC_MEM_FLAGS_AQL_QUEUE_MEM );
1202
+ (* mem )-> aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM );
1202
1203
1203
1204
/* Workaround for AQL queue wraparound bug. Map the same
1204
1205
* memory twice. That means we only actually allocate half
@@ -1680,10 +1681,12 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
1680
1681
1681
1682
INIT_LIST_HEAD (& (* mem )-> bo_va_list );
1682
1683
mutex_init (& (* mem )-> lock );
1684
+
1683
1685
(* mem )-> alloc_flags =
1684
1686
((bo -> preferred_domains & AMDGPU_GEM_DOMAIN_VRAM ) ?
1685
- ALLOC_MEM_FLAGS_VRAM : ALLOC_MEM_FLAGS_GTT ) |
1686
- ALLOC_MEM_FLAGS_WRITABLE | ALLOC_MEM_FLAGS_EXECUTABLE ;
1687
+ KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT )
1688
+ | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE
1689
+ | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE ;
1687
1690
1688
1691
(* mem )-> bo = amdgpu_bo_ref (bo );
1689
1692
(* mem )-> va = va ;
0 commit comments