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Li Maalexdeucher
Li Ma
authored and
alexdeucher
committed
drm/amd/swsmu: enable more Pstates profile levels for SMU v14.0.0 and v14.0.1
V1: This patch enables following UMD stable Pstates profile levels for power_dpm_force_performance_level interface. - profile_peak - profile_min_mclk - profile_min_sclk - profile_standard V2: Fix conflict with commit "drm/amd/pm: smu v14.0.4 reuse smu v14.0.0 dpmtable " V3: Add VCLK1 and DCLK1 support for SMU V14.0.1 And avoid to set VCLK1 and DCLK1 for SMU v14.0.0 Signed-off-by: Li Ma <[email protected]> Reviewed-by: Tim Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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‎drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

Lines changed: 142 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -65,6 +65,10 @@
6565

6666
#define SMU_MALL_PG_CONFIG_DEFAULT SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON
6767

68+
#define SMU_14_0_0_UMD_PSTATE_GFXCLK 700
69+
#define SMU_14_0_0_UMD_PSTATE_SOCCLK 678
70+
#define SMU_14_0_0_UMD_PSTATE_FCLK 1800
71+
6872
#define FEATURE_MASK(feature) (1ULL << feature)
6973
#define SMC_DPM_FEATURE ( \
7074
FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
@@ -725,7 +729,7 @@ static int smu_v14_0_common_get_dpm_freq_by_index(struct smu_context *smu,
725729
{
726730
if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
727731
smu_v14_0_1_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq);
728-
else
732+
else if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1)
729733
smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq);
730734

731735
return 0;
@@ -818,9 +822,11 @@ static int smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
818822
break;
819823
case SMU_MCLK:
820824
case SMU_UCLK:
821-
case SMU_FCLK:
822825
max_dpm_level = 0;
823826
break;
827+
case SMU_FCLK:
828+
max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
829+
break;
824830
case SMU_SOCCLK:
825831
max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
826832
break;
@@ -855,7 +861,7 @@ static int smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
855861
min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
856862
break;
857863
case SMU_FCLK:
858-
min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
864+
min_dpm_level = 0;
859865
break;
860866
case SMU_SOCCLK:
861867
min_dpm_level = 0;
@@ -936,9 +942,11 @@ static int smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
936942
break;
937943
case SMU_MCLK:
938944
case SMU_UCLK:
939-
case SMU_FCLK:
940945
max_dpm_level = 0;
941946
break;
947+
case SMU_FCLK:
948+
max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
949+
break;
942950
case SMU_SOCCLK:
943951
max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
944952
break;
@@ -969,7 +977,7 @@ static int smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
969977
min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
970978
break;
971979
case SMU_FCLK:
972-
min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
980+
min_dpm_level = 0;
973981
break;
974982
case SMU_SOCCLK:
975983
min_dpm_level = 0;
@@ -1001,7 +1009,7 @@ static int smu_v14_0_common_get_dpm_ultimate_freq(struct smu_context *smu,
10011009
{
10021010
if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
10031011
smu_v14_0_1_get_dpm_ultimate_freq(smu, clk_type, min, max);
1004-
else
1012+
else if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1)
10051013
smu_v14_0_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
10061014

10071015
return 0;
@@ -1020,9 +1028,15 @@ static int smu_v14_0_0_get_current_clk_freq(struct smu_context *smu,
10201028
case SMU_VCLK:
10211029
member_type = METRICS_AVERAGE_VCLK;
10221030
break;
1031+
case SMU_VCLK1:
1032+
member_type = METRICS_AVERAGE_VCLK1;
1033+
break;
10231034
case SMU_DCLK:
10241035
member_type = METRICS_AVERAGE_DCLK;
10251036
break;
1037+
case SMU_DCLK1:
1038+
member_type = METRICS_AVERAGE_DCLK1;
1039+
break;
10261040
case SMU_MCLK:
10271041
member_type = METRICS_AVERAGE_UCLK;
10281042
break;
@@ -1106,7 +1120,7 @@ static int smu_v14_0_common_get_dpm_level_count(struct smu_context *smu,
11061120
{
11071121
if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
11081122
smu_v14_0_1_get_dpm_level_count(smu, clk_type, count);
1109-
else
1123+
else if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1)
11101124
smu_v14_0_0_get_dpm_level_count(smu, clk_type, count);
11111125

11121126
return 0;
@@ -1250,6 +1264,8 @@ static int smu_v14_0_0_force_clk_levels(struct smu_context *smu,
12501264
case SMU_FCLK:
12511265
case SMU_VCLK:
12521266
case SMU_DCLK:
1267+
case SMU_VCLK1:
1268+
case SMU_DCLK1:
12531269
ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
12541270
if (ret)
12551271
break;
@@ -1268,42 +1284,122 @@ static int smu_v14_0_0_force_clk_levels(struct smu_context *smu,
12681284
return ret;
12691285
}
12701286

1271-
static int smu_v14_0_0_set_performance_level(struct smu_context *smu,
1287+
static int smu_v14_0_common_get_dpm_profile_freq(struct smu_context *smu,
1288+
enum amd_dpm_forced_level level,
1289+
enum smu_clk_type clk_type,
1290+
uint32_t *min_clk,
1291+
uint32_t *max_clk)
1292+
{
1293+
uint32_t clk_limit = 0;
1294+
int ret = 0;
1295+
1296+
switch (clk_type) {
1297+
case SMU_GFXCLK:
1298+
case SMU_SCLK:
1299+
clk_limit = SMU_14_0_0_UMD_PSTATE_GFXCLK;
1300+
if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
1301+
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &clk_limit);
1302+
else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
1303+
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit, NULL);
1304+
break;
1305+
case SMU_SOCCLK:
1306+
clk_limit = SMU_14_0_0_UMD_PSTATE_SOCCLK;
1307+
if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
1308+
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &clk_limit);
1309+
break;
1310+
case SMU_FCLK:
1311+
clk_limit = SMU_14_0_0_UMD_PSTATE_FCLK;
1312+
if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
1313+
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &clk_limit);
1314+
else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
1315+
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, &clk_limit, NULL);
1316+
break;
1317+
case SMU_VCLK:
1318+
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &clk_limit);
1319+
break;
1320+
case SMU_VCLK1:
1321+
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK1, NULL, &clk_limit);
1322+
break;
1323+
case SMU_DCLK:
1324+
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &clk_limit);
1325+
break;
1326+
case SMU_DCLK1:
1327+
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK1, NULL, &clk_limit);
1328+
break;
1329+
default:
1330+
ret = -EINVAL;
1331+
break;
1332+
}
1333+
*min_clk = *max_clk = clk_limit;
1334+
return ret;
1335+
}
1336+
1337+
static int smu_v14_0_common_set_performance_level(struct smu_context *smu,
12721338
enum amd_dpm_forced_level level)
12731339
{
12741340
struct amdgpu_device *adev = smu->adev;
12751341
uint32_t sclk_min = 0, sclk_max = 0;
12761342
uint32_t fclk_min = 0, fclk_max = 0;
12771343
uint32_t socclk_min = 0, socclk_max = 0;
1344+
uint32_t vclk_min = 0, vclk_max = 0;
1345+
uint32_t dclk_min = 0, dclk_max = 0;
1346+
uint32_t vclk1_min = 0, vclk1_max = 0;
1347+
uint32_t dclk1_min = 0, dclk1_max = 0;
12781348
int ret = 0;
12791349

12801350
switch (level) {
12811351
case AMD_DPM_FORCED_LEVEL_HIGH:
12821352
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
12831353
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max);
12841354
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max);
1355+
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_max);
1356+
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_max);
1357+
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK1, NULL, &vclk1_max);
1358+
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK1, NULL, &dclk1_max);
12851359
sclk_min = sclk_max;
12861360
fclk_min = fclk_max;
12871361
socclk_min = socclk_max;
1362+
vclk_min = vclk_max;
1363+
dclk_min = dclk_max;
1364+
vclk1_min = vclk1_max;
1365+
dclk1_min = dclk1_max;
12881366
break;
12891367
case AMD_DPM_FORCED_LEVEL_LOW:
12901368
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
12911369
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL);
12921370
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL);
1371+
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, NULL);
1372+
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, NULL);
1373+
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK1, &vclk1_min, NULL);
1374+
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK1, &dclk1_min, NULL);
12931375
sclk_max = sclk_min;
12941376
fclk_max = fclk_min;
12951377
socclk_max = socclk_min;
1378+
vclk_max = vclk_min;
1379+
dclk_max = dclk_min;
1380+
vclk1_max = vclk1_min;
1381+
dclk1_max = dclk1_min;
12961382
break;
12971383
case AMD_DPM_FORCED_LEVEL_AUTO:
12981384
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
12991385
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max);
13001386
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max);
1387+
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, &vclk_max);
1388+
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, &dclk_max);
1389+
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK1, &vclk1_min, &vclk1_max);
1390+
smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK1, &dclk1_min, &dclk1_max);
13011391
break;
13021392
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
13031393
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
13041394
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
13051395
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1306-
/* Temporarily do nothing since the optimal clocks haven't been provided yet */
1396+
smu_v14_0_common_get_dpm_profile_freq(smu, level, SMU_SCLK, &sclk_min, &sclk_max);
1397+
smu_v14_0_common_get_dpm_profile_freq(smu, level, SMU_FCLK, &fclk_min, &fclk_max);
1398+
smu_v14_0_common_get_dpm_profile_freq(smu, level, SMU_SOCCLK, &socclk_min, &socclk_max);
1399+
smu_v14_0_common_get_dpm_profile_freq(smu, level, SMU_VCLK, &vclk_min, &vclk_max);
1400+
smu_v14_0_common_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max);
1401+
smu_v14_0_common_get_dpm_profile_freq(smu, level, SMU_VCLK1, &vclk1_min, &vclk1_max);
1402+
smu_v14_0_common_get_dpm_profile_freq(smu, level, SMU_DCLK1, &dclk1_min, &dclk1_max);
13071403
break;
13081404
case AMD_DPM_FORCED_LEVEL_MANUAL:
13091405
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
@@ -1343,6 +1439,42 @@ static int smu_v14_0_0_set_performance_level(struct smu_context *smu,
13431439
return ret;
13441440
}
13451441

1442+
if (vclk_min && vclk_max) {
1443+
ret = smu_v14_0_0_set_soft_freq_limited_range(smu,
1444+
SMU_VCLK,
1445+
vclk_min,
1446+
vclk_max);
1447+
if (ret)
1448+
return ret;
1449+
}
1450+
1451+
if (vclk1_min && vclk1_max) {
1452+
ret = smu_v14_0_0_set_soft_freq_limited_range(smu,
1453+
SMU_VCLK1,
1454+
vclk1_min,
1455+
vclk1_max);
1456+
if (ret)
1457+
return ret;
1458+
}
1459+
1460+
if (dclk_min && dclk_max) {
1461+
ret = smu_v14_0_0_set_soft_freq_limited_range(smu,
1462+
SMU_DCLK,
1463+
dclk_min,
1464+
dclk_max);
1465+
if (ret)
1466+
return ret;
1467+
}
1468+
1469+
if (dclk1_min && dclk1_max) {
1470+
ret = smu_v14_0_0_set_soft_freq_limited_range(smu,
1471+
SMU_DCLK1,
1472+
dclk1_min,
1473+
dclk1_max);
1474+
if (ret)
1475+
return ret;
1476+
}
1477+
13461478
return ret;
13471479
}
13481480

@@ -1520,7 +1652,7 @@ static const struct pptable_funcs smu_v14_0_0_ppt_funcs = {
15201652
.od_edit_dpm_table = smu_v14_0_od_edit_dpm_table,
15211653
.print_clk_levels = smu_v14_0_0_print_clk_levels,
15221654
.force_clk_levels = smu_v14_0_0_force_clk_levels,
1523-
.set_performance_level = smu_v14_0_0_set_performance_level,
1655+
.set_performance_level = smu_v14_0_common_set_performance_level,
15241656
.set_fine_grain_gfx_freq_parameters = smu_v14_0_common_set_fine_grain_gfx_freq_parameters,
15251657
.set_gfx_power_up_by_imu = smu_v14_0_set_gfx_power_up_by_imu,
15261658
.dpm_set_vpe_enable = smu_v14_0_0_set_vpe_enable,

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