Skip to content

Commit 1f05f65

Browse files
mrnukegroeck
authored andcommitted
hwmon: (tps23861) fix byte order in resistance register
The tps23861 registers are little-endian, and regmap_read_bulk() does not do byte order conversion. On BE machines, the bytes were swapped, and the interpretation of the resistance value was incorrect. To make it work on both big and little-endian machines, use le16_to_cpu() to convert the resitance register to host byte order. Signed-off-by: Alexandru Gagniuc <[email protected]> Fixes: fff7b8a ("hwmon: add Texas Instruments TPS23861 driver") Cc: [email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Guenter Roeck <[email protected]>
1 parent 7e18e42 commit 1f05f65

File tree

1 file changed

+6
-4
lines changed

1 file changed

+6
-4
lines changed

drivers/hwmon/tps23861.c

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -493,18 +493,20 @@ static char *tps23861_port_poe_plus_status(struct tps23861_data *data, int port)
493493

494494
static int tps23861_port_resistance(struct tps23861_data *data, int port)
495495
{
496-
u16 regval;
496+
unsigned int raw_val;
497+
__le16 regval;
497498

498499
regmap_bulk_read(data->regmap,
499500
PORT_1_RESISTANCE_LSB + PORT_N_RESISTANCE_LSB_OFFSET * (port - 1),
500501
&regval,
501502
2);
502503

503-
switch (FIELD_GET(PORT_RESISTANCE_RSN_MASK, regval)) {
504+
raw_val = le16_to_cpu(regval);
505+
switch (FIELD_GET(PORT_RESISTANCE_RSN_MASK, raw_val)) {
504506
case PORT_RESISTANCE_RSN_OTHER:
505-
return (FIELD_GET(PORT_RESISTANCE_MASK, regval) * RESISTANCE_LSB) / 10000;
507+
return (FIELD_GET(PORT_RESISTANCE_MASK, raw_val) * RESISTANCE_LSB) / 10000;
506508
case PORT_RESISTANCE_RSN_LOW:
507-
return (FIELD_GET(PORT_RESISTANCE_MASK, regval) * RESISTANCE_LSB_LOW) / 10000;
509+
return (FIELD_GET(PORT_RESISTANCE_MASK, raw_val) * RESISTANCE_LSB_LOW) / 10000;
508510
case PORT_RESISTANCE_RSN_SHORT:
509511
case PORT_RESISTANCE_RSN_OPEN:
510512
default:

0 commit comments

Comments
 (0)