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Merge tag 'omap-for-v5.16/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/soc
SoC changes for omaps for v5.16 Few non-urgent comment typo fixes and few changes to drop unused auxdata. Then a series of changes to drop some a pile of old unused defines. These can be now dropped for the SoCs that have been updated to use devicetree data with drivers/clock and drivers/soc device drivers. * tag 'omap-for-v5.16/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2+: Drop unused CM defines for am3 ARM: OMAP2+: Drop unused CM and SCRM defines for omap4 ARM: OMAP2+: Drop unused CM and SCRM defines for omap5 ARM: OMAP2+: Drop unused CM defines for dra7 ARM: OMAP2+: Drop unused PRM defines for am3 ARM: OMAP2+: Drop unused PRM defines for am4 ARM: OMAP2+: Drop unused PRM defines for omap4 ARM: OMAP2+: Drop unused PRM defines for omap5 ARM: OMAP2+: Drop unused PRM defines for dra7 ARM: OMAP2+: Fix comment typo ARM: OMAP2+: Fix typo in some comments ARM: OMAP2+: Drop unused old auxdata for dra7x_evm_mmc_quirk() ARM: OMAP2+: Drop old unused omap5_uevm_legacy_init() Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2 parents 5816b3e + e60150d commit 1f1c232

18 files changed

+6
-4292
lines changed

‎arch/arm/mach-omap2/cm-regbits-44xx.h

Lines changed: 0 additions & 101 deletions
Original file line numberDiff line numberDiff line change
@@ -20,71 +20,11 @@
2020
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
2121

2222
#define OMAP4430_ABE_STATDEP_SHIFT 3
23-
#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0)
24-
#define OMAP4430_CLKSEL_SHIFT 24
25-
#define OMAP4430_CLKSEL_WIDTH 0x1
26-
#define OMAP4430_CLKSEL_MASK (1 << 24)
27-
#define OMAP4430_CLKSEL_0_0_SHIFT 0
28-
#define OMAP4430_CLKSEL_0_0_WIDTH 0x1
29-
#define OMAP4430_CLKSEL_0_1_SHIFT 0
30-
#define OMAP4430_CLKSEL_0_1_WIDTH 0x2
31-
#define OMAP4430_CLKSEL_24_25_SHIFT 24
32-
#define OMAP4430_CLKSEL_24_25_WIDTH 0x2
33-
#define OMAP4430_CLKSEL_60M_SHIFT 24
34-
#define OMAP4430_CLKSEL_60M_WIDTH 0x1
35-
#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24
36-
#define OMAP4430_CLKSEL_AESS_FCLK_WIDTH 0x1
37-
#define OMAP4430_CLKSEL_CORE_SHIFT 0
38-
#define OMAP4430_CLKSEL_CORE_WIDTH 0x1
39-
#define OMAP4430_CLKSEL_DIV_SHIFT 24
40-
#define OMAP4430_CLKSEL_DIV_WIDTH 0x1
41-
#define OMAP4430_CLKSEL_FCLK_SHIFT 24
42-
#define OMAP4430_CLKSEL_FCLK_WIDTH 0x2
43-
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25
44-
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH 0x1
45-
#define OMAP4430_CLKSEL_L3_SHIFT 4
46-
#define OMAP4430_CLKSEL_L3_WIDTH 0x1
47-
#define OMAP4430_CLKSEL_L4_SHIFT 8
48-
#define OMAP4430_CLKSEL_L4_WIDTH 0x1
49-
#define OMAP4430_CLKSEL_OPP_SHIFT 0
50-
#define OMAP4430_CLKSEL_OPP_WIDTH 0x2
51-
#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27
52-
#define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH 0x3
53-
#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24)
54-
#define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24)
55-
#define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24)
56-
#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24)
57-
#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24
58-
#define OMAP4430_CLKSEL_UTMI_P1_WIDTH 0x1
59-
#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25
60-
#define OMAP4430_CLKSEL_UTMI_P2_WIDTH 0x1
6123
#define OMAP4430_CLKTRCTRL_SHIFT 0
6224
#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0)
63-
#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23
64-
#define OMAP4430_DPLL_BYP_CLKSEL_WIDTH 0x1
65-
#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0)
66-
#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8
67-
#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10)
68-
#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0
69-
#define OMAP4430_DPLL_CLKOUT_DIV_WIDTH 0x5
70-
#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
71-
#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
72-
#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
73-
#define OMAP4430_DPLL_DIV_MASK (0x7f << 0)
74-
#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0)
75-
#define OMAP4430_DPLL_EN_MASK (0x7 << 0)
76-
#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10)
77-
#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8)
78-
#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8)
79-
#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11)
80-
#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24)
8125
#define OMAP4430_DSS_STATDEP_SHIFT 8
8226
#define OMAP4430_DUCATI_STATDEP_SHIFT 0
8327
#define OMAP4430_GFX_STATDEP_SHIFT 10
84-
#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
85-
#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
86-
#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
87-
#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0)
8828
#define OMAP4430_IDLEST_SHIFT 16
8929
#define OMAP4430_IDLEST_MASK (0x3 << 16)
9030
#define OMAP4430_IVAHD_STATDEP_SHIFT 2
@@ -98,46 +38,5 @@
9838
#define OMAP4430_MEMIF_STATDEP_SHIFT 4
9939
#define OMAP4430_MODULEMODE_SHIFT 0
10040
#define OMAP4430_MODULEMODE_MASK (0x3 << 0)
101-
#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9
102-
#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8
103-
#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8
104-
#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8
105-
#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8
106-
#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8
107-
#define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8
108-
#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8
109-
#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9
110-
#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10
111-
#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15
112-
#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
113-
#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
114-
#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
115-
#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
116-
#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8
117-
#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9
118-
#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8
119-
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10
120-
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11
121-
#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10
122-
#define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8
123-
#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11
124-
#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
125-
#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
126-
#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
127-
#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
128-
#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
129-
#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
130-
#define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8
131-
#define OMAP4430_PAD_CLKS_GATE_SHIFT 8
132-
#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20
133-
#define OMAP4430_PMD_STM_MUX_CTRL_WIDTH 0x2
134-
#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22
135-
#define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH 0x2
136-
#define OMAP4430_SCALE_FCLK_SHIFT 0
137-
#define OMAP4430_SCALE_FCLK_WIDTH 0x1
138-
#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10
139-
#define OMAP4430_ST_DPLL_CLK_MASK (1 << 0)
140-
#define OMAP4430_SYS_CLKSEL_SHIFT 0
141-
#define OMAP4430_SYS_CLKSEL_WIDTH 0x3
14241
#define OMAP4430_TESLA_STATDEP_SHIFT 1
14342
#endif

‎arch/arm/mach-omap2/cm1_44xx.h

Lines changed: 0 additions & 174 deletions
Original file line numberDiff line numberDiff line change
@@ -34,184 +34,10 @@
3434
#define OMAP4430_CM1_MPU_INST 0x0300
3535
#define OMAP4430_CM1_TESLA_INST 0x0400
3636
#define OMAP4430_CM1_ABE_INST 0x0500
37-
#define OMAP4430_CM1_RESTORE_INST 0x0e00
38-
#define OMAP4430_CM1_INSTR_INST 0x0f00
3937

4038
/* CM1 clockdomain register offsets (from instance start) */
4139
#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
4240
#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
4341
#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
4442

45-
/* CM1 */
46-
47-
/* CM1.OCP_SOCKET_CM1 register offsets */
48-
#define OMAP4_REVISION_CM1_OFFSET 0x0000
49-
#define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000)
50-
#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040
51-
#define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040)
52-
53-
/* CM1.CKGEN_CM1 register offsets */
54-
#define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000
55-
#define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000)
56-
#define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008
57-
#define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008)
58-
#define OMAP4_CM_DLL_CTRL_OFFSET 0x0010
59-
#define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010)
60-
#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
61-
#define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020)
62-
#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
63-
#define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024)
64-
#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
65-
#define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028)
66-
#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
67-
#define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c)
68-
#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
69-
#define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030)
70-
#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
71-
#define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034)
72-
#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038
73-
#define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038)
74-
#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c
75-
#define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c)
76-
#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040
77-
#define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040)
78-
#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044
79-
#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
80-
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
81-
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
82-
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
83-
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
84-
#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050
85-
#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
86-
#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
87-
#define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060)
88-
#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
89-
#define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064)
90-
#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
91-
#define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068)
92-
#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
93-
#define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c)
94-
#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
95-
#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
96-
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
97-
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
98-
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
99-
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
100-
#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
101-
#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
102-
#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
103-
#define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0)
104-
#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
105-
#define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4)
106-
#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
107-
#define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8)
108-
#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
109-
#define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac)
110-
#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8
111-
#define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8)
112-
#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc
113-
#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
114-
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
115-
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
116-
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
117-
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
118-
#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
119-
#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
120-
#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
121-
#define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0)
122-
#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
123-
#define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4)
124-
#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
125-
#define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8)
126-
#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
127-
#define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec)
128-
#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
129-
#define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0)
130-
#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
131-
#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
132-
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
133-
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
134-
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
135-
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
136-
#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120
137-
#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
138-
#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124
139-
#define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124)
140-
#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128
141-
#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128)
142-
#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c
143-
#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c)
144-
#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130
145-
#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130)
146-
#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138
147-
#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138)
148-
#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c
149-
#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c)
150-
#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140
151-
#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
152-
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148
153-
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
154-
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
155-
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
156-
#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
157-
#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
158-
#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
159-
#define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164)
160-
#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
161-
#define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170)
162-
#define OMAP4_CM_RESTORE_ST_OFFSET 0x0180
163-
#define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180)
164-
165-
/* CM1.MPU_CM1 register offsets */
166-
#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000
167-
#define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000)
168-
#define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004
169-
#define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004)
170-
#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008
171-
#define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008)
172-
#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
173-
#define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020)
174-
175-
/* CM1.TESLA_CM1 register offsets */
176-
#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000
177-
#define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000)
178-
#define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004
179-
#define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004)
180-
#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008
181-
#define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008)
182-
#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020
183-
#define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020)
184-
185-
/* CM1.ABE_CM1 register offsets */
186-
#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000
187-
#define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000)
188-
#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020
189-
#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020)
190-
#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028
191-
#define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028)
192-
#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030
193-
#define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030)
194-
#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038
195-
#define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038)
196-
#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040
197-
#define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040)
198-
#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048
199-
#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048)
200-
#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050
201-
#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050)
202-
#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058
203-
#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058)
204-
#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060
205-
#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060)
206-
#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068
207-
#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068)
208-
#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070
209-
#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070)
210-
#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078
211-
#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078)
212-
#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080
213-
#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080)
214-
#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
215-
#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
216-
21743
#endif

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