@@ -217,24 +217,24 @@ static int rzv2h_wdt_probe(struct platform_device *pdev)
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if (IS_ERR (priv -> base ))
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return PTR_ERR (priv -> base );
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- priv -> pclk = devm_clk_get_prepared (& pdev -> dev , "pclk" );
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+ priv -> pclk = devm_clk_get_prepared (dev , "pclk" );
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if (IS_ERR (priv -> pclk ))
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- return dev_err_probe (& pdev -> dev , PTR_ERR (priv -> pclk ), "no pclk" );
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+ return dev_err_probe (dev , PTR_ERR (priv -> pclk ), "no pclk" );
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- priv -> oscclk = devm_clk_get_prepared (& pdev -> dev , "oscclk" );
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+ priv -> oscclk = devm_clk_get_prepared (dev , "oscclk" );
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if (IS_ERR (priv -> oscclk ))
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- return dev_err_probe (& pdev -> dev , PTR_ERR (priv -> oscclk ), "no oscclk" );
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+ return dev_err_probe (dev , PTR_ERR (priv -> oscclk ), "no oscclk" );
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- priv -> rstc = devm_reset_control_get_exclusive (& pdev -> dev , NULL );
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+ priv -> rstc = devm_reset_control_get_exclusive (dev , NULL );
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if (IS_ERR (priv -> rstc ))
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- return dev_err_probe (& pdev -> dev , PTR_ERR (priv -> rstc ),
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+ return dev_err_probe (dev , PTR_ERR (priv -> rstc ),
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"failed to get cpg reset" );
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priv -> wdev .max_hw_heartbeat_ms = (MILLI * MAX_TIMEOUT_CYCLES * CLOCK_DIV_BY_256 ) /
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clk_get_rate (priv -> oscclk );
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dev_dbg (dev , "max hw timeout of %dms\n" , priv -> wdev .max_hw_heartbeat_ms );
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- ret = devm_pm_runtime_enable (& pdev -> dev );
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+ ret = devm_pm_runtime_enable (dev );
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if (ret )
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return ret ;
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@@ -251,7 +251,7 @@ static int rzv2h_wdt_probe(struct platform_device *pdev)
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if (ret )
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dev_warn (dev , "Specified timeout invalid, using default" );
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- return devm_watchdog_register_device (& pdev -> dev , & priv -> wdev );
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+ return devm_watchdog_register_device (dev , & priv -> wdev );
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}
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static const struct of_device_id rzv2h_wdt_ids [] = {
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