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pfiserShawn Guo
pfiser
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Shawn Guo
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arm64: dts: freescale: Add PHYTEC phyBOARD-Nash-i.MX93 support
Add initial support for PHYTEC phyBOARD-Nash-i.MX93 board [1] based on the PHYTEC phyCORE-i.MX93 SoM (System-on-Module) [2]. Supported board features: * ADC * CAN * Ethernet * EEPROM * RTC * RS-232/RS-485 * SD-card * TPM 2.0 * USB For more details see the product pages for the development kit and the SoM: [1] https://www.phytec.eu/en/produkte/development-kits/phyboard-nash/ [2] https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ Signed-off-by: Primoz Fiser <[email protected]> Reviewed-by: Wadim Egorov <[email protected]> Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
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‎arch/arm64/boot/dts/freescale/Makefile

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@@ -322,6 +322,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-i3c.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx93-14x14-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx93-kontron-bl-osm-s.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb

‎arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2025 PHYTEC Messtechnik GmbH
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* Author: Primoz Fiser <[email protected]>
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*
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* Product homepage:
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* https://www.phytec.eu/en/produkte/development-kits/phyboard-nash/
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*/
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/dts-v1/;
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#include <dt-bindings/net/ti-dp83867.h>
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#include "imx93-phycore-som.dtsi"
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/ {
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model = "PHYTEC phyBOARD-Nash-i.MX93";
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compatible = "phytec,imx93-phyboard-nash", "phytec,imx93-phycore-som",
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"fsl,imx93";
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aliases {
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ethernet0 = &fec;
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ethernet1 = &eqos;
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rtc0 = &i2c_rtc;
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rtc1 = &bbnsm_rtc;
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};
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chosen {
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stdout-path = &lpuart1;
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};
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flexcan1_tc: can-phy0 {
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compatible = "ti,tcan1042";
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#phy-cells = <0>;
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max-bitrate = <8000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1_tc>;
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standby-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VCC_SD";
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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};
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reg_vcc_1v8: regulator-vcc-1v8 {
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compatible = "regulator-fixed";
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regulator-name = "VCC1V8";
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regulator-max-microvolt = <1800000>;
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regulator-min-microvolt = <1800000>;
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};
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reg_vref_1v8: regulator-adc-vref {
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compatible = "regulator-fixed";
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regulator-name = "VREF_1V8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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};
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/* ADC */
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&adc1 {
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vref-supply = <&reg_vref_1v8>;
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status = "okay";
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};
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/* Ethernet */
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&eqos {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos>;
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phy-mode = "rgmii-id";
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phy-handle = <&ethphy2>;
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status = "okay";
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};
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&mdio {
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ethphy2: ethernet-phy@2 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <2>;
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interrupt-parent = <&gpio3>;
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interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
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ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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};
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};
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/* CAN */
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&flexcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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phys = <&flexcan1_tc>;
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status = "okay";
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};
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/* I2C2 */
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&lpi2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpi2c2>;
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status = "okay";
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/* RTC */
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i2c_rtc: rtc@52 {
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compatible = "microcrystal,rv3028";
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reg = <0x52>;
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interrupt-parent = <&gpio4>;
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interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rtc>;
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trickle-resistor-ohms = <3000>;
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wakeup-source;
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};
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/* EEPROM */
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eeprom@54 {
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compatible = "atmel,24c32";
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reg = <0x54>;
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pagesize = <32>;
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vcc-supply = <&reg_vcc_1v8>;
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};
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};
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/* SPI6 */
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&lpspi6 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpspi6>;
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cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
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status = "okay";
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/* TPM */
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tpm@0 {
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compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
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reg = <0>;
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interrupt-parent = <&gpio2>;
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interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_tpm>;
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spi-max-frequency = <10000000>;
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};
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};
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/* Console */
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&lpuart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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/* RS-232/RS-485 */
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&lpuart7 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart7>;
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status = "okay";
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};
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/* USB */
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&usbotg1 {
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disable-over-current;
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dr_mode = "otg";
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status = "okay";
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};
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&usbotg2 {
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disable-over-current;
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dr_mode = "host";
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status = "okay";
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};
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/* SD-Card */
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
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cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
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vmmc-supply = <&reg_usdhc2_vmmc>;
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bus-width = <4>;
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disable-wp;
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no-mmc;
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no-sdio;
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status = "okay";
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};
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&iomuxc {
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pinctrl_eqos: eqosgrp {
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fsl,pins = <
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MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
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MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
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MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
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MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
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MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
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MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
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MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e
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MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e
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MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x50e
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MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x50e
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MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
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MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x50e
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MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1002
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>;
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};
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pinctrl_flexcan1: flexcan1grp {
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fsl,pins = <
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MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
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MX93_PAD_PDM_CLK__CAN1_TX 0x1382
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>;
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};
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pinctrl_flexcan1_tc: flexcan1tcgrp {
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fsl,pins = <
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MX93_PAD_ENET2_TD3__GPIO4_IO16 0x31e
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>;
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};
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pinctrl_lpi2c2: lpi2c2grp {
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fsl,pins = <
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MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
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MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
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>;
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};
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pinctrl_lpspi6: lpspi6grp {
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fsl,pins = <
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MX93_PAD_GPIO_IO00__GPIO2_IO00 0x386
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MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe
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MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x386
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MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x386
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>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
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fsl,pins = <
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MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
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>;
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};
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pinctrl_rtc: rtcgrp {
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fsl,pins = <
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MX93_PAD_ENET2_RD2__GPIO4_IO26 0x31e
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>;
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};
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pinctrl_tpm: tpmgrp {
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fsl,pins = <
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MX93_PAD_GPIO_IO17__GPIO2_IO17 0x31e
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
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MX93_PAD_UART1_TXD__LPUART1_TX 0x30e
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>;
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};
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pinctrl_uart7: uart7grp {
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fsl,pins = <
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MX93_PAD_GPIO_IO08__LPUART7_TX 0x30e
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MX93_PAD_GPIO_IO09__LPUART7_RX 0x31e
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MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x31e
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MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e
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>;
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};
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pinctrl_usdhc2_cd: usdhc2cdgrp {
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fsl,pins = <
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MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
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>;
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};
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/* need to config the SION for data and cmd pad, refer to ERR052021 */
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pinctrl_usdhc2_default: usdhc2grp {
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fsl,pins = <
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MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e
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MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000178e
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MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001386
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MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001386
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MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001386
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MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
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MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
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>;
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};
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/* need to config the SION for data and cmd pad, refer to ERR052021 */
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pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
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fsl,pins = <
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MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e
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MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
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MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e
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MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e
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MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e
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MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013be
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MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
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>;
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};
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/* need to config the SION for data and cmd pad, refer to ERR052021 */
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pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
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fsl,pins = <
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MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e
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MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
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MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e
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MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e
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MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e
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MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e
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MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
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>;
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};
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};

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