Revert "drm/amd/display: Do not set DRR on pipe commit"

AMD-aric · alexdeucher · commit 1fa0d424a1d5 · 2023-03-01T22:43:58.000-05:00
This reverts commit 4f1b5e7. [Why & How] Original change causes a regression. Revert until fix is available. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -998,5 +998,8 @@ void dcn30_prepare_bandwidth(struct dc *dc,
 			dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
 
 	dcn20_prepare_bandwidth(dc, context);
+
+	dc_dmub_srv_p_state_delegate(dc,
+		context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching, context);
 }
 

Original file line number	Diff line number	Diff line change
`@@ -998,5 +998,8 @@ void dcn30_prepare_bandwidth(struct dc *dc,`
`998`	`998`	`dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);`
`999`	`999`
`1000`	`1000`	`dcn20_prepare_bandwidth(dc, context);`
	`1001`	`+`
	`1002`	`+ dc_dmub_srv_p_state_delegate(dc,`
	`1003`	`+ context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching, context);`
`1001`	`1004`	`}`
`1002`	`1005`