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dt-bindings: dma: Convert fsl,elo*-dma to YAML
The devicetree bindings for Freescale DMA engines have so far existed as a text file. This patch converts them to YAML, and specifies all the compatible strings currently in use in arch/powerpc/boot/dts. Signed-off-by: J. Neuschäfer <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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‎Documentation/devicetree/bindings/dma/fsl,elo-dma.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/fsl,elo-dma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Elo DMA Controller
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maintainers:
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- J. Neuschäfer <[email protected]>
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description:
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This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
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series chips such as mpc8315, mpc8349, mpc8379 etc.
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properties:
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compatible:
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items:
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- enum:
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- fsl,mpc8313-dma
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- fsl,mpc8315-dma
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- fsl,mpc8323-dma
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- fsl,mpc8347-dma
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- fsl,mpc8349-dma
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- fsl,mpc8360-dma
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- fsl,mpc8377-dma
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- fsl,mpc8378-dma
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- fsl,mpc8379-dma
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- const: fsl,elo-dma
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reg:
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items:
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- description:
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DMA General Status Register, i.e. DGSR which contains status for
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all the 4 DMA channels.
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cell-index:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Controller index. 0 for controller @ 0x8100.
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ranges: true
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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interrupts:
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maxItems: 1
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description: Controller interrupt.
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required:
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- compatible
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- reg
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patternProperties:
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"^dma-channel@[0-9a-f]+$":
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type: object
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additionalProperties: false
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properties:
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compatible:
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oneOf:
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# native DMA channel
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- items:
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- enum:
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- fsl,mpc8315-dma-channel
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- fsl,mpc8323-dma-channel
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- fsl,mpc8347-dma-channel
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- fsl,mpc8349-dma-channel
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- fsl,mpc8360-dma-channel
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- fsl,mpc8377-dma-channel
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- fsl,mpc8378-dma-channel
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- fsl,mpc8379-dma-channel
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- const: fsl,elo-dma-channel
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# audio DMA channel, see fsl,ssi.yaml
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- const: fsl,ssi-dma-channel
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reg:
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maxItems: 1
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cell-index:
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description: DMA channel index starts at 0.
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interrupts:
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maxItems: 1
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description:
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Per-channel interrupt. Only necessary if no controller interrupt has
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been provided.
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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dma@82a8 {
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compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
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reg = <0x82a8 4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x8100 0x1a4>;
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interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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reg = <0 0x80>;
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cell-index = <0>;
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interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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...

‎Documentation/devicetree/bindings/dma/fsl,elo3-dma.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/fsl,elo3-dma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Elo3 DMA Controller
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maintainers:
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- J. Neuschäfer <[email protected]>
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description:
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DMA controller which has same function as EloPlus except that Elo3 has 8
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channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx
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series chips, such as t1040, t4240, b4860.
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properties:
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compatible:
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const: fsl,elo3-dma
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reg:
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items:
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- description:
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DMA General Status Registers starting from DGSR0, for channel 1~4
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- description:
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DMA General Status Registers starting from DGSR1, for channel 5~8
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ranges: true
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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interrupts:
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maxItems: 1
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patternProperties:
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"^dma-channel@[0-9a-f]+$":
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type: object
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additionalProperties: false
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properties:
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compatible:
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enum:
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# native DMA channel
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- fsl,eloplus-dma-channel
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# audio DMA channel, see fsl,ssi.yaml
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- fsl,ssi-dma-channel
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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description:
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Per-channel interrupt. Only necessary if no controller interrupt has
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been provided.
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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dma@100300 {
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compatible = "fsl,elo3-dma";
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reg = <0x100300 0x4>,
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<0x100600 0x4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x100100 0x500>;
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dma-channel@0 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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interrupts = <28 IRQ_TYPE_EDGE_FALLING 0 0>;
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};
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dma-channel@80 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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interrupts = <29 IRQ_TYPE_EDGE_FALLING 0 0>;
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};
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dma-channel@100 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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interrupts = <30 IRQ_TYPE_EDGE_FALLING 0 0>;
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};
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dma-channel@180 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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interrupts = <31 IRQ_TYPE_EDGE_FALLING 0 0>;
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};
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dma-channel@300 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x300 0x80>;
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interrupts = <76 IRQ_TYPE_EDGE_FALLING 0 0>;
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};
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dma-channel@380 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x380 0x80>;
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interrupts = <77 IRQ_TYPE_EDGE_FALLING 0 0>;
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};
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dma-channel@400 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x400 0x80>;
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interrupts = <78 IRQ_TYPE_EDGE_FALLING 0 0>;
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};
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dma-channel@480 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x480 0x80>;
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interrupts = <79 IRQ_TYPE_EDGE_FALLING 0 0>;
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};
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};
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...

‎Documentation/devicetree/bindings/dma/fsl,eloplus-dma.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/fsl,eloplus-dma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale EloPlus DMA Controller
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maintainers:
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- J. Neuschäfer <[email protected]>
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description:
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This is a 4-channel DMA controller with extended addresses and chaining,
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mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as
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mpc8540, mpc8641 p4080, bsc9131 etc.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- fsl,mpc8540-dma
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- fsl,mpc8541-dma
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- fsl,mpc8548-dma
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- fsl,mpc8555-dma
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- fsl,mpc8560-dma
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- fsl,mpc8572-dma
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- fsl,mpc8641-dma
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- const: fsl,eloplus-dma
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- const: fsl,eloplus-dma
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reg:
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items:
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- description:
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DMA General Status Register, i.e. DGSR which contains
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status for all the 4 DMA channels
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cell-index:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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controller index. 0 for controller @ 0x21000, 1 for controller @ 0xc000
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ranges: true
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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interrupts:
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maxItems: 1
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description: Controller interrupt.
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patternProperties:
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"^dma-channel@[0-9a-f]+$":
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type: object
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additionalProperties: false
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properties:
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compatible:
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oneOf:
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# native DMA channel
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- items:
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- enum:
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- fsl,mpc8540-dma-channel
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- fsl,mpc8541-dma-channel
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- fsl,mpc8548-dma-channel
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- fsl,mpc8555-dma-channel
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- fsl,mpc8560-dma-channel
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- fsl,mpc8572-dma-channel
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- const: fsl,eloplus-dma-channel
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# audio DMA channel, see fsl,ssi.yaml
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- const: fsl,ssi-dma-channel
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reg:
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maxItems: 1
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cell-index:
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description: DMA channel index starts at 0.
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interrupts:
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maxItems: 1
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description:
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Per-channel interrupt. Only necessary if no controller interrupt has
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been provided.
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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dma@21300 {
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compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
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reg = <0x21300 4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
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reg = <0 0x80>;
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cell-index = <0>;
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interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupts = <22 IRQ_TYPE_EDGE_FALLING>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
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};
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};
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...

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