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bjorn-helgaasbjorn-helgaas
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Merge branch 'pci/controller/dw-rockchip'
- Check only PCIE_LINKUP, not LTSSM status, to determine whether the link is up (Shawn Lin) - Increase N_FTS (used in L0s->L0 transitions) and enable ASPM L0s for Root Complex and Endpoint modes (Shawn Lin) - Hide the broken ATS Capability in rockchip_pcie_ep_init() instead of rockchip_pcie_ep_pre_init() so it stays hidden after PERST# resets non-sticky registers (Shawn Lin) - Remove unused PCIE_CLIENT_GENERAL_DEBUG definition (Hans Zhang) - Organize register and bitfield definitions logically (Hans Zhang) - Use rockchip_pcie_link_up() to check link up instead of open coding, and use GENMASK() and FIELD_GET() when possible (Hans Zhang) - Call phy_power_off() before phy_exit() in rockchip_pcie_phy_deinit() (Diederik de Haas) - Return bool (not int) for link-up check in dw_pcie_ops.link_up() and armada8k, dra7xx, dw-rockchip, exynos, histb, keembay, keystone, kirin, meson, qcom, qcom-ep, rcar_gen4, spear13xx, tegra194, uniphier, visconti (Hans Zhang) - Return bool (not int) for link-up check in mobiveil_pab_ops.link_up() and layerscape-gen4, mobiveil (Hans Zhang) - Simplify j721e link-up check (Hans Zhang) - Convert pci-host-common to a library so platforms that don't need native host controller drivers don't need to include these helper functions (Manivannan Sadhasivam) * pci/controller/dw-rockchip: PCI: qcom: Replace PERST# sleep time with proper macro PCI: dw-rockchip: Replace PERST# sleep time with proper macro PCI: host-common: Convert to library for host controller drivers PCI: cadence: Simplify J721e link status check PCI: mobiveil: Return bool from link up check PCI: dwc: Return bool from link up check PCI: dw-rockchip: Fix PHY function call sequence in rockchip_pcie_phy_deinit() PCI: dw-rockchip: Use rockchip_pcie_link_up() to check link up instead of open coding PCI: dw-rockchip: Reorganize register and bitfield definitions PCI: dw-rockchip: Remove unused PCIE_CLIENT_GENERAL_DEBUG definition PCI: dw-rockchip: Move rockchip_pcie_ep_hide_broken_ats_cap_rk3588() to dw_pcie_ep_ops::init() PCI: dw-rockchip: Enable ASPM L0s capability for both RC and EP modes PCI: dw-rockchip: Remove PCIE_L0S_ENTRY check from rockchip_pcie_link_up() # Conflicts: # drivers/pci/controller/pcie-apple.c # include/linux/pci-ecam.h
2 parents 3f0b362 + ec49e25 commit 2027962

31 files changed

+137
-109
lines changed

‎drivers/pci/controller/Kconfig

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,10 @@
33
menu "PCI controller drivers"
44
depends on PCI
55

6+
config PCI_HOST_COMMON
7+
tristate
8+
select PCI_ECAM
9+
610
config PCI_AARDVARK
711
tristate "Aardvark PCIe controller"
812
depends on (ARCH_MVEBU && ARM64) || COMPILE_TEST
@@ -119,10 +123,6 @@ config PCI_FTPCI100
119123
depends on OF
120124
default ARCH_GEMINI
121125

122-
config PCI_HOST_COMMON
123-
tristate
124-
select PCI_ECAM
125-
126126
config PCI_HOST_GENERIC
127127
tristate "Generic PCI host controller"
128128
depends on OF

‎drivers/pci/controller/cadence/pci-j721e.c

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -164,11 +164,7 @@ static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie)
164164
u32 reg;
165165

166166
reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS);
167-
reg &= LINK_STATUS;
168-
if (reg == LINK_UP_DL_COMPLETED)
169-
return true;
170-
171-
return false;
167+
return (reg & LINK_STATUS) == LINK_UP_DL_COMPLETED;
172168
}
173169

174170
static const struct cdns_pcie_ops j721e_pcie_ops = {

‎drivers/pci/controller/dwc/pci-dra7xx.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -118,12 +118,12 @@ static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 cpu_addr)
118118
return cpu_addr & DRA7XX_CPU_TO_BUS_ADDR;
119119
}
120120

121-
static int dra7xx_pcie_link_up(struct dw_pcie *pci)
121+
static bool dra7xx_pcie_link_up(struct dw_pcie *pci)
122122
{
123123
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
124124
u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
125125

126-
return !!(reg & LINK_UP);
126+
return reg & LINK_UP;
127127
}
128128

129129
static void dra7xx_pcie_stop_link(struct dw_pcie *pci)

‎drivers/pci/controller/dwc/pci-exynos.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -209,12 +209,12 @@ static struct pci_ops exynos_pci_ops = {
209209
.write = exynos_pcie_wr_own_conf,
210210
};
211211

212-
static int exynos_pcie_link_up(struct dw_pcie *pci)
212+
static bool exynos_pcie_link_up(struct dw_pcie *pci)
213213
{
214214
struct exynos_pcie *ep = to_exynos_pcie(pci);
215215
u32 val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_RDLH_LINKUP);
216216

217-
return (val & PCIE_ELBI_XMLH_LINKUP);
217+
return val & PCIE_ELBI_XMLH_LINKUP;
218218
}
219219

220220
static int exynos_pcie_host_init(struct dw_pcie_rp *pp)

‎drivers/pci/controller/dwc/pci-keystone.c

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -492,13 +492,12 @@ static struct pci_ops ks_pcie_ops = {
492492
* @pci: A pointer to the dw_pcie structure which holds the DesignWare PCIe host
493493
* controller driver information.
494494
*/
495-
static int ks_pcie_link_up(struct dw_pcie *pci)
495+
static bool ks_pcie_link_up(struct dw_pcie *pci)
496496
{
497497
u32 val;
498498

499499
val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0);
500-
val &= PORT_LOGIC_LTSSM_STATE_MASK;
501-
return (val == PORT_LOGIC_LTSSM_STATE_L0);
500+
return (val & PORT_LOGIC_LTSSM_STATE_MASK) == PORT_LOGIC_LTSSM_STATE_L0;
502501
}
503502

504503
static void ks_pcie_stop_link(struct dw_pcie *pci)

‎drivers/pci/controller/dwc/pci-meson.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -335,7 +335,7 @@ static struct pci_ops meson_pci_ops = {
335335
.write = pci_generic_config_write,
336336
};
337337

338-
static int meson_pcie_link_up(struct dw_pcie *pci)
338+
static bool meson_pcie_link_up(struct dw_pcie *pci)
339339
{
340340
struct meson_pcie *mp = to_meson_pcie(pci);
341341
struct device *dev = pci->dev;
@@ -363,15 +363,15 @@ static int meson_pcie_link_up(struct dw_pcie *pci)
363363
dev_dbg(dev, "speed_okay\n");
364364

365365
if (smlh_up && rdlh_up && ltssm_up && speed_okay)
366-
return 1;
366+
return true;
367367

368368
cnt++;
369369

370370
udelay(10);
371371
} while (cnt < WAIT_LINKUP_TIMEOUT);
372372

373373
dev_err(dev, "error: wait linkup timeout\n");
374-
return 0;
374+
return false;
375375
}
376376

377377
static int meson_pcie_host_init(struct dw_pcie_rp *pp)

‎drivers/pci/controller/dwc/pcie-armada8k.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -139,18 +139,18 @@ static int armada8k_pcie_setup_phys(struct armada8k_pcie *pcie)
139139
return ret;
140140
}
141141

142-
static int armada8k_pcie_link_up(struct dw_pcie *pci)
142+
static bool armada8k_pcie_link_up(struct dw_pcie *pci)
143143
{
144144
u32 reg;
145145
u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
146146

147147
reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_STATUS_REG);
148148

149149
if ((reg & mask) == mask)
150-
return 1;
150+
return true;
151151

152152
dev_dbg(pci->dev, "No link detected (Global-Status: 0x%08x).\n", reg);
153-
return 0;
153+
return false;
154154
}
155155

156156
static int armada8k_pcie_start_link(struct dw_pcie *pci)

‎drivers/pci/controller/dwc/pcie-designware.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -711,7 +711,7 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci)
711711
}
712712
EXPORT_SYMBOL_GPL(dw_pcie_wait_for_link);
713713

714-
int dw_pcie_link_up(struct dw_pcie *pci)
714+
bool dw_pcie_link_up(struct dw_pcie *pci)
715715
{
716716
u32 val;
717717

‎drivers/pci/controller/dwc/pcie-designware.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -462,7 +462,7 @@ struct dw_pcie_ops {
462462
size_t size, u32 val);
463463
void (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
464464
size_t size, u32 val);
465-
int (*link_up)(struct dw_pcie *pcie);
465+
bool (*link_up)(struct dw_pcie *pcie);
466466
enum dw_pcie_ltssm (*get_ltssm)(struct dw_pcie *pcie);
467467
int (*start_link)(struct dw_pcie *pcie);
468468
void (*stop_link)(struct dw_pcie *pcie);
@@ -537,7 +537,7 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val);
537537
u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size);
538538
void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
539539
void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
540-
int dw_pcie_link_up(struct dw_pcie *pci);
540+
bool dw_pcie_link_up(struct dw_pcie *pci);
541541
void dw_pcie_upconfig_setup(struct dw_pcie *pci);
542542
int dw_pcie_wait_for_link(struct dw_pcie *pci);
543543
int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,

‎drivers/pci/controller/dwc/pcie-dw-rockchip.c

Lines changed: 63 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88
* Author: Simon Xue <[email protected]>
99
*/
1010

11+
#include <linux/bitfield.h>
1112
#include <linux/clk.h>
1213
#include <linux/gpio/consumer.h>
1314
#include <linux/irqchip/chained_irq.h>
@@ -21,6 +22,7 @@
2122
#include <linux/regmap.h>
2223
#include <linux/reset.h>
2324

25+
#include "../../pci.h"
2426
#include "pcie-designware.h"
2527

2628
/*
@@ -33,26 +35,36 @@
3335

3436
#define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
3537

36-
#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40)
37-
#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0)
38-
#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc)
39-
#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8)
40-
#define PCIE_CLIENT_INTR_STATUS_MISC 0x10
41-
#define PCIE_CLIENT_INTR_MASK_MISC 0x24
42-
#define PCIE_SMLH_LINKUP BIT(16)
43-
#define PCIE_RDLH_LINKUP BIT(17)
44-
#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP)
45-
#define PCIE_RDLH_LINK_UP_CHGED BIT(1)
46-
#define PCIE_LINK_REQ_RST_NOT_INT BIT(2)
47-
#define PCIE_L0S_ENTRY 0x11
48-
#define PCIE_CLIENT_GENERAL_CONTROL 0x0
38+
/* General Control Register */
39+
#define PCIE_CLIENT_GENERAL_CON 0x0
40+
#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40)
41+
#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0)
42+
#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc)
43+
#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8)
44+
45+
/* Interrupt Status Register Related to Legacy Interrupt */
4946
#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8
47+
48+
/* Interrupt Status Register Related to Miscellaneous Operation */
49+
#define PCIE_CLIENT_INTR_STATUS_MISC 0x10
50+
#define PCIE_RDLH_LINK_UP_CHGED BIT(1)
51+
#define PCIE_LINK_REQ_RST_NOT_INT BIT(2)
52+
53+
/* Interrupt Mask Register Related to Legacy Interrupt */
5054
#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c
51-
#define PCIE_CLIENT_GENERAL_DEBUG 0x104
55+
56+
/* Interrupt Mask Register Related to Miscellaneous Operation */
57+
#define PCIE_CLIENT_INTR_MASK_MISC 0x24
58+
59+
/* Hot Reset Control Register */
5260
#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
61+
#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
62+
63+
/* LTSSM Status Register */
5364
#define PCIE_CLIENT_LTSSM_STATUS 0x300
54-
#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
55-
#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0)
65+
#define PCIE_LINKUP 0x3
66+
#define PCIE_LINKUP_MASK GENMASK(17, 16)
67+
#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0)
5668

5769
struct rockchip_pcie {
5870
struct dw_pcie pci;
@@ -163,25 +175,36 @@ static u32 rockchip_pcie_get_ltssm(struct rockchip_pcie *rockchip)
163175
static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)
164176
{
165177
rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,
166-
PCIE_CLIENT_GENERAL_CONTROL);
178+
PCIE_CLIENT_GENERAL_CON);
167179
}
168180

169181
static void rockchip_pcie_disable_ltssm(struct rockchip_pcie *rockchip)
170182
{
171183
rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DISABLE_LTSSM,
172-
PCIE_CLIENT_GENERAL_CONTROL);
184+
PCIE_CLIENT_GENERAL_CON);
173185
}
174186

175-
static int rockchip_pcie_link_up(struct dw_pcie *pci)
187+
static bool rockchip_pcie_link_up(struct dw_pcie *pci)
176188
{
177189
struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
178190
u32 val = rockchip_pcie_get_ltssm(rockchip);
179191

180-
if ((val & PCIE_LINKUP) == PCIE_LINKUP &&
181-
(val & PCIE_LTSSM_STATUS_MASK) == PCIE_L0S_ENTRY)
182-
return 1;
192+
return FIELD_GET(PCIE_LINKUP_MASK, val) == PCIE_LINKUP;
193+
}
183194

184-
return 0;
195+
static void rockchip_pcie_enable_l0s(struct dw_pcie *pci)
196+
{
197+
u32 cap, lnkcap;
198+
199+
/* Enable L0S capability for all SoCs */
200+
cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
201+
if (cap) {
202+
lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
203+
lnkcap |= PCI_EXP_LNKCAP_ASPM_L0S;
204+
dw_pcie_dbi_ro_wr_en(pci);
205+
dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);
206+
dw_pcie_dbi_ro_wr_dis(pci);
207+
}
185208
}
186209

187210
static int rockchip_pcie_start_link(struct dw_pcie *pci)
@@ -202,7 +225,7 @@ static int rockchip_pcie_start_link(struct dw_pcie *pci)
202225
* We need more extra time as before, rather than setting just
203226
* 100us as we don't know how long should the device need to reset.
204227
*/
205-
msleep(100);
228+
msleep(PCIE_T_PVPERL_MS);
206229
gpiod_set_value_cansleep(rockchip->rst_gpio, 1);
207230

208231
return 0;
@@ -233,6 +256,8 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)
233256
irq_set_chained_handler_and_data(irq, rockchip_pcie_intx_handler,
234257
rockchip);
235258

259+
rockchip_pcie_enable_l0s(pci);
260+
236261
return 0;
237262
}
238263

@@ -263,16 +288,14 @@ static void rockchip_pcie_ep_hide_broken_ats_cap_rk3588(struct dw_pcie_ep *ep)
263288
dev_err(dev, "failed to hide ATS capability\n");
264289
}
265290

266-
static void rockchip_pcie_ep_pre_init(struct dw_pcie_ep *ep)
267-
{
268-
rockchip_pcie_ep_hide_broken_ats_cap_rk3588(ep);
269-
}
270-
271291
static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep)
272292
{
273293
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
274294
enum pci_barno bar;
275295

296+
rockchip_pcie_enable_l0s(pci);
297+
rockchip_pcie_ep_hide_broken_ats_cap_rk3588(ep);
298+
276299
for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
277300
dw_pcie_ep_reset_bar(pci, bar);
278301
};
@@ -342,7 +365,6 @@ rockchip_pcie_get_features(struct dw_pcie_ep *ep)
342365

343366
static const struct dw_pcie_ep_ops rockchip_pcie_ep_ops = {
344367
.init = rockchip_pcie_ep_init,
345-
.pre_init = rockchip_pcie_ep_pre_init,
346368
.raise_irq = rockchip_pcie_raise_irq,
347369
.get_features = rockchip_pcie_get_features,
348370
};
@@ -410,8 +432,8 @@ static int rockchip_pcie_phy_init(struct rockchip_pcie *rockchip)
410432

411433
static void rockchip_pcie_phy_deinit(struct rockchip_pcie *rockchip)
412434
{
413-
phy_exit(rockchip->phy);
414435
phy_power_off(rockchip->phy);
436+
phy_exit(rockchip->phy);
415437
}
416438

417439
static const struct dw_pcie_ops dw_pcie_ops = {
@@ -426,7 +448,7 @@ static irqreturn_t rockchip_pcie_rc_sys_irq_thread(int irq, void *arg)
426448
struct dw_pcie *pci = &rockchip->pci;
427449
struct dw_pcie_rp *pp = &pci->pp;
428450
struct device *dev = pci->dev;
429-
u32 reg, val;
451+
u32 reg;
430452

431453
reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);
432454
rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
@@ -435,8 +457,7 @@ static irqreturn_t rockchip_pcie_rc_sys_irq_thread(int irq, void *arg)
435457
dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm(rockchip));
436458

437459
if (reg & PCIE_RDLH_LINK_UP_CHGED) {
438-
val = rockchip_pcie_get_ltssm(rockchip);
439-
if ((val & PCIE_LINKUP) == PCIE_LINKUP) {
460+
if (rockchip_pcie_link_up(pci)) {
440461
dev_dbg(dev, "Received Link up event. Starting enumeration!\n");
441462
/* Rescan the bus to enumerate endpoint devices */
442463
pci_lock_rescan_remove();
@@ -453,7 +474,7 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg)
453474
struct rockchip_pcie *rockchip = arg;
454475
struct dw_pcie *pci = &rockchip->pci;
455476
struct device *dev = pci->dev;
456-
u32 reg, val;
477+
u32 reg;
457478

458479
reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);
459480
rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
@@ -467,8 +488,7 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg)
467488
}
468489

469490
if (reg & PCIE_RDLH_LINK_UP_CHGED) {
470-
val = rockchip_pcie_get_ltssm(rockchip);
471-
if ((val & PCIE_LINKUP) == PCIE_LINKUP) {
491+
if (rockchip_pcie_link_up(pci)) {
472492
dev_dbg(dev, "link up\n");
473493
dw_pcie_ep_linkup(&pci->ep);
474494
}
@@ -505,7 +525,7 @@ static int rockchip_pcie_configure_rc(struct platform_device *pdev,
505525
rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
506526

507527
rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE,
508-
PCIE_CLIENT_GENERAL_CONTROL);
528+
PCIE_CLIENT_GENERAL_CON);
509529

510530
pp = &rockchip->pci.pp;
511531
pp->ops = &rockchip_pcie_host_ops;
@@ -551,7 +571,7 @@ static int rockchip_pcie_configure_ep(struct platform_device *pdev,
551571
rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
552572

553573
rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_EP_MODE,
554-
PCIE_CLIENT_GENERAL_CONTROL);
574+
PCIE_CLIENT_GENERAL_CON);
555575

556576
rockchip->pci.ep.ops = &rockchip_pcie_ep_ops;
557577
rockchip->pci.ep.page_size = SZ_64K;
@@ -601,6 +621,10 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
601621
rockchip->pci.ops = &dw_pcie_ops;
602622
rockchip->data = data;
603623

624+
/* Default N_FTS value (210) is broken, override it to 255 */
625+
rockchip->pci.n_fts[0] = 255; /* Gen1 */
626+
rockchip->pci.n_fts[1] = 255; /* Gen2+ */
627+
604628
ret = rockchip_pcie_resource_get(pdev, rockchip);
605629
if (ret)
606630
return ret;

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