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torvaldstorvalds
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Merge tag 'drm-fixes-2024-08-30' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie: "Another week, another set of GPU fixes. amdgpu and vmwgfx leading the charge, then i915 and xe changes along with v3d and some other bits. The TTM revert is due to some stuttering graphical apps probably due to longer stalls while prefaulting. Seems pretty much where I'd expect things, ttm: - revert prefault change, caused stutters aperture: - handle non-VGA devices bettter amdgpu: - SWSMU gaming stability fix - SMU 13.0.7 fix - SWSMU documentation alignment fix - SMU 14.0.x fixes - GC 12.x fix - Display fix - IP discovery fix - SMU 13.0.6 fix i915: - Fix #11195: The external display connect via USB type-C dock stays blank after re-connect the dock - Make DSI backlight work for 2G version of Lenovo Yoga Tab 3 X90F - Move ARL GuC firmware to correct version xe: - Invalidate media_gt TLBs - Fix HWMON i1 power setup write command vmwgfx: - prevent unmapping active read buffers - fix prime with external buffers - disable coherent dumb buffers without 3d v3d: - disable preemption while updating GPU stats" * tag 'drm-fixes-2024-08-30' of https://gitlab.freedesktop.org/drm/kernel: drm/xe/hwmon: Fix WRITE_I1 param from u32 to u16 drm/v3d: Disable preemption while updating GPU stats drm/amd/pm: Drop unsupported features on smu v14_0_2 drm/amd/pm: Add support for new P2S table revision drm/amdgpu: support for gc_info table v1.3 drm/amd/display: avoid using null object of framebuffer drm/amdgpu/gfx12: set UNORD_DISPATCH in compute MQDs drm/amd/pm: update message interface for smu v14.0.2/3 drm/amdgpu/swsmu: always force a state reprogram on init drm/amdgpu/smu13.0.7: print index for profiles drm/amdgpu: align pp_power_profile_mode with kernel docs drm/i915/dp_mst: Fix MST state after a sink reset drm/xe: Invalidate media_gt TLBs drm/i915: ARL requires a newer GSC firmware drm/i915/dsi: Make Lenovo Yoga Tab 3 X90F DMI match less strict video/aperture: optionally match the device in sysfb_disable() drm/vmwgfx: Disable coherent dumb buffers without 3d drm/vmwgfx: Fix prime with external buffers drm/vmwgfx: Prevent unmapping active read buffers Revert "drm/ttm: increase ttm pre-fault value to PMD size"
2 parents 1b5fe53 + 27f5b72 commit 20371ba

35 files changed

+398
-126
lines changed

‎drivers/firmware/sysfb.c

Lines changed: 13 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,8 @@ static struct platform_device *pd;
3939
static DEFINE_MUTEX(disable_lock);
4040
static bool disabled;
4141

42+
static struct device *sysfb_parent_dev(const struct screen_info *si);
43+
4244
static bool sysfb_unregister(void)
4345
{
4446
if (IS_ERR_OR_NULL(pd))
@@ -52,6 +54,7 @@ static bool sysfb_unregister(void)
5254

5355
/**
5456
* sysfb_disable() - disable the Generic System Framebuffers support
57+
* @dev: the device to check if non-NULL
5558
*
5659
* This disables the registration of system framebuffer devices that match the
5760
* generic drivers that make use of the system framebuffer set up by firmware.
@@ -61,17 +64,21 @@ static bool sysfb_unregister(void)
6164
* Context: The function can sleep. A @disable_lock mutex is acquired to serialize
6265
* against sysfb_init(), that registers a system framebuffer device.
6366
*/
64-
void sysfb_disable(void)
67+
void sysfb_disable(struct device *dev)
6568
{
69+
struct screen_info *si = &screen_info;
70+
6671
mutex_lock(&disable_lock);
67-
sysfb_unregister();
68-
disabled = true;
72+
if (!dev || dev == sysfb_parent_dev(si)) {
73+
sysfb_unregister();
74+
disabled = true;
75+
}
6976
mutex_unlock(&disable_lock);
7077
}
7178
EXPORT_SYMBOL_GPL(sysfb_disable);
7279

7380
#if defined(CONFIG_PCI)
74-
static __init bool sysfb_pci_dev_is_enabled(struct pci_dev *pdev)
81+
static bool sysfb_pci_dev_is_enabled(struct pci_dev *pdev)
7582
{
7683
/*
7784
* TODO: Try to integrate this code into the PCI subsystem
@@ -87,13 +94,13 @@ static __init bool sysfb_pci_dev_is_enabled(struct pci_dev *pdev)
8794
return true;
8895
}
8996
#else
90-
static __init bool sysfb_pci_dev_is_enabled(struct pci_dev *pdev)
97+
static bool sysfb_pci_dev_is_enabled(struct pci_dev *pdev)
9198
{
9299
return false;
93100
}
94101
#endif
95102

96-
static __init struct device *sysfb_parent_dev(const struct screen_info *si)
103+
static struct device *sysfb_parent_dev(const struct screen_info *si)
97104
{
98105
struct pci_dev *pdev;
99106

‎drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1500,6 +1500,7 @@ union gc_info {
15001500
struct gc_info_v1_0 v1;
15011501
struct gc_info_v1_1 v1_1;
15021502
struct gc_info_v1_2 v1_2;
1503+
struct gc_info_v1_3 v1_3;
15031504
struct gc_info_v2_0 v2;
15041505
struct gc_info_v2_1 v2_1;
15051506
};
@@ -1558,6 +1559,16 @@ static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
15581559
adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance);
15591560
adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu);
15601561
}
1562+
if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) {
1563+
adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu);
1564+
adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size);
1565+
adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc);
1566+
adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size);
1567+
adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc);
1568+
adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size);
1569+
adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size);
1570+
adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size);
1571+
}
15611572
break;
15621573
case 2:
15631574
adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -240,6 +240,12 @@ struct amdgpu_gfx_config {
240240
uint32_t gc_tcp_size_per_cu;
241241
uint32_t gc_num_cu_per_sqc;
242242
uint32_t gc_tcc_size;
243+
uint32_t gc_tcp_cache_line_size;
244+
uint32_t gc_instruction_cache_size_per_sqc;
245+
uint32_t gc_instruction_cache_line_size;
246+
uint32_t gc_scalar_data_cache_size_per_sqc;
247+
uint32_t gc_scalar_data_cache_line_size;
248+
uint32_t gc_tcc_cache_line_size;
243249
};
244250

245251
struct amdgpu_cu_info {

‎drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3005,7 +3005,7 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
30053005
(order_base_2(prop->queue_size / 4) - 1));
30063006
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
30073007
(order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
3008-
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3008+
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
30093009
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
30103010
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
30113011
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

‎drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -187,6 +187,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd,
187187
m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
188188
m->cp_hqd_pq_control |=
189189
ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;
190+
m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;
190191
pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
191192

192193
m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@
2828
#include <drm/drm_blend.h>
2929
#include <drm/drm_gem_atomic_helper.h>
3030
#include <drm/drm_plane_helper.h>
31+
#include <drm/drm_gem_framebuffer_helper.h>
3132
#include <drm/drm_fourcc.h>
3233

3334
#include "amdgpu.h"
@@ -935,10 +936,14 @@ static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane,
935936
}
936937

937938
afb = to_amdgpu_framebuffer(new_state->fb);
938-
obj = new_state->fb->obj[0];
939+
obj = drm_gem_fb_get_obj(new_state->fb, 0);
940+
if (!obj) {
941+
DRM_ERROR("Failed to get obj from framebuffer\n");
942+
return -EINVAL;
943+
}
944+
939945
rbo = gem_to_amdgpu_bo(obj);
940946
adev = amdgpu_ttm_adev(rbo->tbo.bdev);
941-
942947
r = amdgpu_bo_reserve(rbo, true);
943948
if (r) {
944949
dev_err(adev->dev, "fail to reserve bo (%d)\n", r);

‎drivers/gpu/drm/amd/include/discovery.h

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -258,6 +258,48 @@ struct gc_info_v1_2 {
258258
uint32_t gc_gl2c_per_gpu;
259259
};
260260

261+
struct gc_info_v1_3 {
262+
struct gpu_info_header header;
263+
uint32_t gc_num_se;
264+
uint32_t gc_num_wgp0_per_sa;
265+
uint32_t gc_num_wgp1_per_sa;
266+
uint32_t gc_num_rb_per_se;
267+
uint32_t gc_num_gl2c;
268+
uint32_t gc_num_gprs;
269+
uint32_t gc_num_max_gs_thds;
270+
uint32_t gc_gs_table_depth;
271+
uint32_t gc_gsprim_buff_depth;
272+
uint32_t gc_parameter_cache_depth;
273+
uint32_t gc_double_offchip_lds_buffer;
274+
uint32_t gc_wave_size;
275+
uint32_t gc_max_waves_per_simd;
276+
uint32_t gc_max_scratch_slots_per_cu;
277+
uint32_t gc_lds_size;
278+
uint32_t gc_num_sc_per_se;
279+
uint32_t gc_num_sa_per_se;
280+
uint32_t gc_num_packer_per_sc;
281+
uint32_t gc_num_gl2a;
282+
uint32_t gc_num_tcp_per_sa;
283+
uint32_t gc_num_sdp_interface;
284+
uint32_t gc_num_tcps;
285+
uint32_t gc_num_tcp_per_wpg;
286+
uint32_t gc_tcp_l1_size;
287+
uint32_t gc_num_sqc_per_wgp;
288+
uint32_t gc_l1_instruction_cache_size_per_sqc;
289+
uint32_t gc_l1_data_cache_size_per_sqc;
290+
uint32_t gc_gl1c_per_sa;
291+
uint32_t gc_gl1c_size_per_instance;
292+
uint32_t gc_gl2c_per_gpu;
293+
uint32_t gc_tcp_size_per_cu;
294+
uint32_t gc_tcp_cache_line_size;
295+
uint32_t gc_instruction_cache_size_per_sqc;
296+
uint32_t gc_instruction_cache_line_size;
297+
uint32_t gc_scalar_data_cache_size_per_sqc;
298+
uint32_t gc_scalar_data_cache_line_size;
299+
uint32_t gc_tcc_size;
300+
uint32_t gc_tcc_cache_line_size;
301+
};
302+
261303
struct gc_info_v2_0 {
262304
struct gpu_info_header header;
263305

‎drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

Lines changed: 11 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2224,8 +2224,9 @@ static int smu_bump_power_profile_mode(struct smu_context *smu,
22242224
}
22252225

22262226
static int smu_adjust_power_state_dynamic(struct smu_context *smu,
2227-
enum amd_dpm_forced_level level,
2228-
bool skip_display_settings)
2227+
enum amd_dpm_forced_level level,
2228+
bool skip_display_settings,
2229+
bool force_update)
22292230
{
22302231
int ret = 0;
22312232
int index = 0;
@@ -2254,7 +2255,7 @@ static int smu_adjust_power_state_dynamic(struct smu_context *smu,
22542255
}
22552256
}
22562257

2257-
if (smu_dpm_ctx->dpm_level != level) {
2258+
if (force_update || smu_dpm_ctx->dpm_level != level) {
22582259
ret = smu_asic_set_performance_level(smu, level);
22592260
if (ret) {
22602261
dev_err(smu->adev->dev, "Failed to set performance level!");
@@ -2265,13 +2266,12 @@ static int smu_adjust_power_state_dynamic(struct smu_context *smu,
22652266
smu_dpm_ctx->dpm_level = level;
22662267
}
22672268

2268-
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
2269-
smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
2269+
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
22702270
index = fls(smu->workload_mask);
22712271
index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
22722272
workload[0] = smu->workload_setting[index];
22732273

2274-
if (smu->power_profile_mode != workload[0])
2274+
if (force_update || smu->power_profile_mode != workload[0])
22752275
smu_bump_power_profile_mode(smu, workload, 0);
22762276
}
22772277

@@ -2292,11 +2292,13 @@ static int smu_handle_task(struct smu_context *smu,
22922292
ret = smu_pre_display_config_changed(smu);
22932293
if (ret)
22942294
return ret;
2295-
ret = smu_adjust_power_state_dynamic(smu, level, false);
2295+
ret = smu_adjust_power_state_dynamic(smu, level, false, false);
22962296
break;
22972297
case AMD_PP_TASK_COMPLETE_INIT:
2298+
ret = smu_adjust_power_state_dynamic(smu, level, true, true);
2299+
break;
22982300
case AMD_PP_TASK_READJUST_POWER_STATE:
2299-
ret = smu_adjust_power_state_dynamic(smu, level, true);
2301+
ret = smu_adjust_power_state_dynamic(smu, level, true, false);
23002302
break;
23012303
default:
23022304
break;
@@ -2343,8 +2345,7 @@ static int smu_switch_power_profile(void *handle,
23432345
workload[0] = smu->workload_setting[index];
23442346
}
23452347

2346-
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
2347-
smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
2348+
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
23482349
smu_bump_power_profile_mode(smu, workload, 0);
23492350

23502351
return 0;

‎drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_2_ppsmc.h

Lines changed: 14 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -92,7 +92,6 @@
9292

9393
//Resets
9494
#define PPSMC_MSG_PrepareMp1ForUnload 0x2E
95-
#define PPSMC_MSG_Mode1Reset 0x2F
9695

9796
//Set SystemVirtual DramAddrHigh
9897
#define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x30
@@ -119,11 +118,12 @@
119118

120119
//STB to dram log
121120
#define PPSMC_MSG_DumpSTBtoDram 0x3D
122-
#define PPSMC_MSG_STBtoDramLogSetDramAddrHigh 0x3E
123-
#define PPSMC_MSG_STBtoDramLogSetDramAddrLow 0x3F
121+
#define PPSMC_MSG_STBtoDramLogSetDramAddress 0x3E
122+
#define PPSMC_MSG_DummyUndefined 0x3F
124123
#define PPSMC_MSG_STBtoDramLogSetDramSize 0x40
125124
#define PPSMC_MSG_SetOBMTraceBufferLogging 0x41
126125

126+
#define PPSMC_MSG_UseProfilingMode 0x42
127127
#define PPSMC_MSG_AllowGfxDcs 0x43
128128
#define PPSMC_MSG_DisallowGfxDcs 0x44
129129
#define PPSMC_MSG_EnableAudioStutterWA 0x45
@@ -135,6 +135,16 @@
135135
#define PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel 0x4B
136136
#define PPSMC_MSG_SetPriorityDeltaGain 0x4C
137137
#define PPSMC_MSG_AllowIHHostInterrupt 0x4D
138+
#define PPSMC_MSG_EnableShadowDpm 0x4E
138139
#define PPSMC_MSG_Mode3Reset 0x4F
139-
#define PPSMC_Message_Count 0x50
140+
#define PPSMC_MSG_SetDriverDramAddr 0x50
141+
#define PPSMC_MSG_SetToolsDramAddr 0x51
142+
#define PPSMC_MSG_TransferTableSmu2DramWithAddr 0x52
143+
#define PPSMC_MSG_TransferTableDram2SmuWithAddr 0x53
144+
#define PPSMC_MSG_GetAllRunningSmuFeatures 0x54
145+
#define PPSMC_MSG_GetSvi3Voltage 0x55
146+
#define PPSMC_MSG_UpdatePolicy 0x56
147+
#define PPSMC_MSG_ExtPwrConnSupport 0x57
148+
#define PPSMC_MSG_PreloadSwPstateForUclkOverDrive 0x58
149+
#define PPSMC_Message_Count 0x59
140150
#endif

‎drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -121,6 +121,7 @@ struct mca_ras_info {
121121

122122
#define P2S_TABLE_ID_A 0x50325341
123123
#define P2S_TABLE_ID_X 0x50325358
124+
#define P2S_TABLE_ID_3 0x50325303
124125

125126
// clang-format off
126127
static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COUNT] = {
@@ -271,14 +272,18 @@ static int smu_v13_0_6_init_microcode(struct smu_context *smu)
271272
struct amdgpu_device *adev = smu->adev;
272273
uint32_t p2s_table_id = P2S_TABLE_ID_A;
273274
int ret = 0, i, p2stable_count;
275+
int var = (adev->pdev->device & 0xF);
274276
char ucode_prefix[15];
275277

276278
/* No need to load P2S tables in IOV mode */
277279
if (amdgpu_sriov_vf(adev))
278280
return 0;
279281

280-
if (!(adev->flags & AMD_IS_APU))
282+
if (!(adev->flags & AMD_IS_APU)) {
281283
p2s_table_id = P2S_TABLE_ID_X;
284+
if (var == 0x5)
285+
p2s_table_id = P2S_TABLE_ID_3;
286+
}
282287

283288
amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix,
284289
sizeof(ucode_prefix));

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