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tejaskuxrodrigovivi
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drm/i915/gt: Use hw_engine_masks as reset_domains
We need a way to reset engines by their reset domains. This change sets up way to fetch reset domains of each engine globally. Changes since V1: - Use static reset domain array - Ville and Tvrtko - Use BUG_ON at appropriate place - Tvrtko Signed-off-by: Tejas Upadhyay <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20211206081026.4024401-1-tejaskumarx.surendrakumar.upadhyay@intel.com
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+35
-27
lines changed

3 files changed

+35
-27
lines changed

drivers/gpu/drm/i915/gt/intel_engine_cs.c

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -325,6 +325,38 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id,
325325
engine->id = id;
326326
engine->legacy_idx = INVALID_ENGINE;
327327
engine->mask = BIT(id);
328+
if (GRAPHICS_VER(gt->i915) >= 11) {
329+
static const u32 engine_reset_domains[] = {
330+
[RCS0] = GEN11_GRDOM_RENDER,
331+
[BCS0] = GEN11_GRDOM_BLT,
332+
[VCS0] = GEN11_GRDOM_MEDIA,
333+
[VCS1] = GEN11_GRDOM_MEDIA2,
334+
[VCS2] = GEN11_GRDOM_MEDIA3,
335+
[VCS3] = GEN11_GRDOM_MEDIA4,
336+
[VCS4] = GEN11_GRDOM_MEDIA5,
337+
[VCS5] = GEN11_GRDOM_MEDIA6,
338+
[VCS6] = GEN11_GRDOM_MEDIA7,
339+
[VCS7] = GEN11_GRDOM_MEDIA8,
340+
[VECS0] = GEN11_GRDOM_VECS,
341+
[VECS1] = GEN11_GRDOM_VECS2,
342+
[VECS2] = GEN11_GRDOM_VECS3,
343+
[VECS3] = GEN11_GRDOM_VECS4,
344+
};
345+
GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
346+
!engine_reset_domains[id]);
347+
engine->reset_domain = engine_reset_domains[id];
348+
} else {
349+
static const u32 engine_reset_domains[] = {
350+
[RCS0] = GEN6_GRDOM_RENDER,
351+
[BCS0] = GEN6_GRDOM_BLT,
352+
[VCS0] = GEN6_GRDOM_MEDIA,
353+
[VCS1] = GEN8_GRDOM_MEDIA2,
354+
[VECS0] = GEN6_GRDOM_VECS,
355+
};
356+
GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
357+
!engine_reset_domains[id]);
358+
engine->reset_domain = engine_reset_domains[id];
359+
}
328360
engine->i915 = i915;
329361
engine->gt = gt;
330362
engine->uncore = gt->uncore;

drivers/gpu/drm/i915/gt/intel_engine_types.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -318,6 +318,7 @@ struct intel_engine_cs {
318318
unsigned int guc_id;
319319

320320
intel_engine_mask_t mask;
321+
u32 reset_domain;
321322
/**
322323
* @logical_mask: logical mask of engine, reported to user space via
323324
* query IOCTL and used to communicate with the GuC in logical space.

drivers/gpu/drm/i915/gt/intel_reset.c

Lines changed: 2 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -297,13 +297,6 @@ static int gen6_reset_engines(struct intel_gt *gt,
297297
intel_engine_mask_t engine_mask,
298298
unsigned int retry)
299299
{
300-
static const u32 hw_engine_mask[] = {
301-
[RCS0] = GEN6_GRDOM_RENDER,
302-
[BCS0] = GEN6_GRDOM_BLT,
303-
[VCS0] = GEN6_GRDOM_MEDIA,
304-
[VCS1] = GEN8_GRDOM_MEDIA2,
305-
[VECS0] = GEN6_GRDOM_VECS,
306-
};
307300
struct intel_engine_cs *engine;
308301
u32 hw_mask;
309302

@@ -314,8 +307,7 @@ static int gen6_reset_engines(struct intel_gt *gt,
314307

315308
hw_mask = 0;
316309
for_each_engine_masked(engine, gt, engine_mask, tmp) {
317-
GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
318-
hw_mask |= hw_engine_mask[engine->id];
310+
hw_mask |= engine->reset_domain;
319311
}
320312
}
321313

@@ -492,22 +484,6 @@ static int gen11_reset_engines(struct intel_gt *gt,
492484
intel_engine_mask_t engine_mask,
493485
unsigned int retry)
494486
{
495-
static const u32 hw_engine_mask[] = {
496-
[RCS0] = GEN11_GRDOM_RENDER,
497-
[BCS0] = GEN11_GRDOM_BLT,
498-
[VCS0] = GEN11_GRDOM_MEDIA,
499-
[VCS1] = GEN11_GRDOM_MEDIA2,
500-
[VCS2] = GEN11_GRDOM_MEDIA3,
501-
[VCS3] = GEN11_GRDOM_MEDIA4,
502-
[VCS4] = GEN11_GRDOM_MEDIA5,
503-
[VCS5] = GEN11_GRDOM_MEDIA6,
504-
[VCS6] = GEN11_GRDOM_MEDIA7,
505-
[VCS7] = GEN11_GRDOM_MEDIA8,
506-
[VECS0] = GEN11_GRDOM_VECS,
507-
[VECS1] = GEN11_GRDOM_VECS2,
508-
[VECS2] = GEN11_GRDOM_VECS3,
509-
[VECS3] = GEN11_GRDOM_VECS4,
510-
};
511487
struct intel_engine_cs *engine;
512488
intel_engine_mask_t tmp;
513489
u32 reset_mask, unlock_mask = 0;
@@ -518,8 +494,7 @@ static int gen11_reset_engines(struct intel_gt *gt,
518494
} else {
519495
reset_mask = 0;
520496
for_each_engine_masked(engine, gt, engine_mask, tmp) {
521-
GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
522-
reset_mask |= hw_engine_mask[engine->id];
497+
reset_mask |= engine->reset_domain;
523498
ret = gen11_lock_sfc(engine, &reset_mask, &unlock_mask);
524499
if (ret)
525500
goto sfc_unlock;

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