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JIaxyga
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clk: qcom: gcc-sm8450: Add SM8475 support
Add support to the SM8475 global clock controller by extending the SM8450 global clock controller, which is almost identical but has some minor differences. Signed-off-by: Danila Tikhonov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
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‎drivers/clk/qcom/Kconfig‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1050,7 +1050,8 @@ config SM_GCC_8450
10501050
depends on ARM64 || COMPILE_TEST
10511051
select QCOM_GDSC
10521052
help
1053-
Support for the global clock controller on SM8450 devices.
1053+
Support for the global clock controller on SM8450 or SM8475
1054+
devices.
10541055
Say Y if you want to use peripheral devices such as UART,
10551056
SPI, I2C, USB, SD/UFS, PCIe etc.
10561057

‎drivers/clk/qcom/gcc-sm8450.c‎

Lines changed: 180 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,8 @@ enum {
2626
P_BI_TCXO,
2727
P_GCC_GPLL0_OUT_EVEN,
2828
P_GCC_GPLL0_OUT_MAIN,
29+
P_SM8475_GCC_GPLL2_OUT_EVEN,
30+
P_SM8475_GCC_GPLL3_OUT_EVEN,
2931
P_GCC_GPLL4_OUT_MAIN,
3032
P_GCC_GPLL9_OUT_MAIN,
3133
P_PCIE_1_PHY_AUX_CLK,
@@ -36,6 +38,15 @@ enum {
3638
P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
3739
};
3840

41+
static struct clk_init_data sm8475_gcc_gpll0_init = {
42+
.name = "gcc_gpll0",
43+
.parent_data = &(const struct clk_parent_data){
44+
.fw_name = "bi_tcxo",
45+
},
46+
.num_parents = 1,
47+
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
48+
};
49+
3950
static struct clk_alpha_pll gcc_gpll0 = {
4051
.offset = 0x0,
4152
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
@@ -53,6 +64,15 @@ static struct clk_alpha_pll gcc_gpll0 = {
5364
},
5465
};
5566

67+
static struct clk_init_data sm8475_gcc_gpll0_out_even_init = {
68+
.name = "gcc_gpll0_out_even",
69+
.parent_hws = (const struct clk_hw*[]) {
70+
&gcc_gpll0.clkr.hw,
71+
},
72+
.num_parents = 1,
73+
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
74+
};
75+
5676
static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
5777
{ 0x1, 2 },
5878
{ }
@@ -75,6 +95,49 @@ static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
7595
},
7696
};
7797

98+
static struct clk_alpha_pll sm8475_gcc_gpll2 = {
99+
.offset = 0x2000,
100+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
101+
.clkr = {
102+
.enable_reg = 0x62018,
103+
.enable_mask = BIT(2),
104+
.hw.init = &(struct clk_init_data){
105+
.name = "gcc_gpll2",
106+
.parent_data = &(const struct clk_parent_data){
107+
.fw_name = "bi_tcxo",
108+
},
109+
.num_parents = 1,
110+
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
111+
},
112+
},
113+
};
114+
115+
static struct clk_alpha_pll sm8475_gcc_gpll3 = {
116+
.offset = 0x3000,
117+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
118+
.clkr = {
119+
.enable_reg = 0x62018,
120+
.enable_mask = BIT(3),
121+
.hw.init = &(struct clk_init_data){
122+
.name = "gcc_gpll3",
123+
.parent_data = &(const struct clk_parent_data){
124+
.fw_name = "bi_tcxo",
125+
},
126+
.num_parents = 1,
127+
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
128+
},
129+
},
130+
};
131+
132+
static struct clk_init_data sm8475_gcc_gpll4_init = {
133+
.name = "gcc_gpll4",
134+
.parent_data = &(const struct clk_parent_data){
135+
.fw_name = "bi_tcxo",
136+
},
137+
.num_parents = 1,
138+
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
139+
};
140+
78141
static struct clk_alpha_pll gcc_gpll4 = {
79142
.offset = 0x4000,
80143
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
@@ -92,6 +155,15 @@ static struct clk_alpha_pll gcc_gpll4 = {
92155
},
93156
};
94157

158+
static struct clk_init_data sm8475_gcc_gpll9_init = {
159+
.name = "gcc_gpll9",
160+
.parent_data = &(const struct clk_parent_data){
161+
.fw_name = "bi_tcxo",
162+
},
163+
.num_parents = 1,
164+
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
165+
};
166+
95167
static struct clk_alpha_pll gcc_gpll9 = {
96168
.offset = 0x9000,
97169
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
@@ -153,6 +225,22 @@ static const struct clk_parent_data gcc_parent_data_3[] = {
153225
{ .fw_name = "bi_tcxo" },
154226
};
155227

228+
static const struct parent_map sm8475_gcc_parent_map_3[] = {
229+
{ P_BI_TCXO, 0 },
230+
{ P_GCC_GPLL0_OUT_MAIN, 1 },
231+
{ P_SM8475_GCC_GPLL2_OUT_EVEN, 2 },
232+
{ P_SM8475_GCC_GPLL3_OUT_EVEN, 3 },
233+
{ P_GCC_GPLL0_OUT_EVEN, 6 },
234+
};
235+
236+
static const struct clk_parent_data sm8475_gcc_parent_data_3[] = {
237+
{ .fw_name = "bi_tcxo" },
238+
{ .hw = &gcc_gpll0.clkr.hw },
239+
{ .hw = &sm8475_gcc_gpll2.clkr.hw },
240+
{ .hw = &sm8475_gcc_gpll3.clkr.hw },
241+
{ .hw = &gcc_gpll0_out_even.clkr.hw },
242+
};
243+
156244
static const struct parent_map gcc_parent_map_5[] = {
157245
{ P_PCIE_1_PHY_AUX_CLK, 0 },
158246
{ P_BI_TCXO, 2 },
@@ -915,6 +1003,16 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
9151003
.clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
9161004
};
9171005

1006+
static const struct freq_tbl sm8475_ftbl_gcc_sdcc2_apps_clk_src[] = {
1007+
F(400000, P_BI_TCXO, 12, 1, 4),
1008+
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1009+
F(37000000, P_GCC_GPLL9_OUT_MAIN, 16, 0, 0),
1010+
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1011+
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1012+
F(148000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1013+
{ }
1014+
};
1015+
9181016
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
9191017
F(400000, P_BI_TCXO, 12, 1, 4),
9201018
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
@@ -963,6 +1061,25 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
9631061
},
9641062
};
9651063

1064+
static const struct freq_tbl sm8475_ftbl_gcc_ufs_phy_axi_clk_src[] = {
1065+
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1066+
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1067+
F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1068+
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1069+
F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0),
1070+
F(806400000, P_SM8475_GCC_GPLL2_OUT_EVEN, 1, 0, 0),
1071+
F(850000000, P_SM8475_GCC_GPLL2_OUT_EVEN, 1, 0, 0),
1072+
{ }
1073+
};
1074+
1075+
static struct clk_init_data sm8475_gcc_ufs_phy_axi_clk_src_init = {
1076+
.name = "gcc_ufs_phy_axi_clk_src",
1077+
.parent_data = sm8475_gcc_parent_data_3,
1078+
.num_parents = ARRAY_SIZE(sm8475_gcc_parent_map_3),
1079+
.flags = CLK_SET_RATE_PARENT,
1080+
.ops = &clk_rcg2_ops,
1081+
};
1082+
9661083
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
9671084
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
9681085
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
@@ -987,6 +1104,24 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
9871104
},
9881105
};
9891106

1107+
static const struct freq_tbl sm8475_ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
1108+
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1109+
F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1110+
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1111+
F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0),
1112+
F(806400000, P_SM8475_GCC_GPLL2_OUT_EVEN, 1, 0, 0),
1113+
F(850000000, P_SM8475_GCC_GPLL2_OUT_EVEN, 1, 0, 0),
1114+
{ }
1115+
};
1116+
1117+
static struct clk_init_data sm8475_gcc_ufs_phy_ice_core_clk_src_init = {
1118+
.name = "gcc_ufs_phy_ice_core_clk_src",
1119+
.parent_data = sm8475_gcc_parent_data_3,
1120+
.num_parents = ARRAY_SIZE(sm8475_gcc_parent_map_3),
1121+
.flags = CLK_SET_RATE_PARENT,
1122+
.ops = &clk_rcg2_ops,
1123+
};
1124+
9901125
static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
9911126
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
9921127
F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
@@ -1032,6 +1167,14 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
10321167
},
10331168
};
10341169

1170+
static struct clk_init_data sm8475_gcc_ufs_phy_unipro_core_clk_src_init = {
1171+
.name = "gcc_ufs_phy_unipro_core_clk_src",
1172+
.parent_data = sm8475_gcc_parent_data_3,
1173+
.num_parents = ARRAY_SIZE(sm8475_gcc_parent_map_3),
1174+
.flags = CLK_SET_RATE_PARENT,
1175+
.ops = &clk_rcg2_ops,
1176+
};
1177+
10351178
static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
10361179
.cmd_rcgr = 0x8708c,
10371180
.mnd_width = 0,
@@ -3166,6 +3309,8 @@ static struct clk_regmap *gcc_sm8450_clocks[] = {
31663309
[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
31673310
[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
31683311
[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
3312+
[SM8475_GCC_GPLL2] = NULL,
3313+
[SM8475_GCC_GPLL3] = NULL,
31693314
};
31703315

31713316
static const struct qcom_reset_map gcc_sm8450_resets[] = {
@@ -3259,6 +3404,7 @@ static const struct qcom_cc_desc gcc_sm8450_desc = {
32593404

32603405
static const struct of_device_id gcc_sm8450_match_table[] = {
32613406
{ .compatible = "qcom,gcc-sm8450" },
3407+
{ .compatible = "qcom,sm8475-gcc" },
32623408
{ }
32633409
};
32643410
MODULE_DEVICE_TABLE(of, gcc_sm8450_match_table);
@@ -3277,6 +3423,39 @@ static int gcc_sm8450_probe(struct platform_device *pdev)
32773423
if (ret)
32783424
return ret;
32793425

3426+
if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-gcc")) {
3427+
/* Update GCC PLL0 */
3428+
gcc_gpll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3429+
gcc_gpll0.clkr.hw.init = &sm8475_gcc_gpll0_init;
3430+
gcc_gpll0_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3431+
gcc_gpll0_out_even.clkr.hw.init = &sm8475_gcc_gpll0_out_even_init;
3432+
3433+
/* Update GCC PLL4 */
3434+
gcc_gpll4.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3435+
gcc_gpll4.clkr.hw.init = &sm8475_gcc_gpll4_init;
3436+
3437+
/* Update GCC PLL9 */
3438+
gcc_gpll9.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3439+
gcc_gpll9.clkr.hw.init = &sm8475_gcc_gpll9_init;
3440+
3441+
gcc_sdcc2_apps_clk_src.freq_tbl = sm8475_ftbl_gcc_sdcc2_apps_clk_src;
3442+
3443+
gcc_ufs_phy_axi_clk_src.parent_map = sm8475_gcc_parent_map_3;
3444+
gcc_ufs_phy_axi_clk_src.freq_tbl = sm8475_ftbl_gcc_ufs_phy_axi_clk_src;
3445+
gcc_ufs_phy_axi_clk_src.clkr.hw.init = &sm8475_gcc_ufs_phy_axi_clk_src_init;
3446+
3447+
gcc_ufs_phy_ice_core_clk_src.parent_map = sm8475_gcc_parent_map_3;
3448+
gcc_ufs_phy_ice_core_clk_src.freq_tbl = sm8475_ftbl_gcc_ufs_phy_ice_core_clk_src;
3449+
gcc_ufs_phy_ice_core_clk_src.clkr.hw.init = &sm8475_gcc_ufs_phy_ice_core_clk_src_init;
3450+
3451+
gcc_ufs_phy_unipro_core_clk_src.parent_map = sm8475_gcc_parent_map_3;
3452+
gcc_ufs_phy_unipro_core_clk_src.freq_tbl = sm8475_ftbl_gcc_ufs_phy_ice_core_clk_src;
3453+
gcc_ufs_phy_unipro_core_clk_src.clkr.hw.init = &sm8475_gcc_ufs_phy_unipro_core_clk_src_init;
3454+
3455+
gcc_sm8450_desc.clks[SM8475_GCC_GPLL2] = &sm8475_gcc_gpll2.clkr;
3456+
gcc_sm8450_desc.clks[SM8475_GCC_GPLL3] = &sm8475_gcc_gpll3.clkr;
3457+
}
3458+
32803459
/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
32813460
regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
32823461

@@ -3312,5 +3491,5 @@ static void __exit gcc_sm8450_exit(void)
33123491
}
33133492
module_exit(gcc_sm8450_exit);
33143493

3315-
MODULE_DESCRIPTION("QTI GCC SM8450 Driver");
3494+
MODULE_DESCRIPTION("QTI GCC SM8450 / SM8475 Driver");
33163495
MODULE_LICENSE("GPL v2");

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