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Krishna chaitanya chundruvinodkoul
Krishna chaitanya chundru
authored and
vinodkoul
committed
phy: qcom: qmp: Add phy register and clk setting for QCS615 PCIe
Add support for GEN3 x1 PCIe PHY found on Qualcomm QCS615 platform. Signed-off-by: Krishna chaitanya chundru <[email protected]> Signed-off-by: Ziyue Zhang <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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‎drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

Lines changed: 105 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -728,6 +728,83 @@ static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_misc_tbl[] = {
728728
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
729729
};
730730

731+
static const struct qmp_phy_init_tbl qcs615_pcie_serdes_tbl[] = {
732+
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
733+
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
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QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
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QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
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QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
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QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
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QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
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QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
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QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
744+
QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
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QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
746+
QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x9),
747+
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x4),
748+
QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
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QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
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QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
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QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
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QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
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QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xd),
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QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x35),
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QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
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QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
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QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x4),
759+
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x30),
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QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
762+
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
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QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
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QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
769+
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
770+
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
771+
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
772+
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
773+
};
774+
775+
static const struct qmp_phy_init_tbl qcs615_pcie_rx_tbl[] = {
776+
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
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QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
778+
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
779+
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
780+
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
781+
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
782+
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
783+
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4),
784+
};
785+
786+
static const struct qmp_phy_init_tbl qcs615_pcie_tx_tbl[] = {
787+
QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
788+
QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
789+
QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
790+
QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
791+
};
792+
793+
static const struct qmp_phy_init_tbl qcs615_pcie_pcs_tbl[] = {
794+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4),
795+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0),
796+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
797+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
798+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
799+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
800+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
801+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
802+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_SIGDET_CNTRL, 0x7),
803+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99),
804+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15),
805+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe),
806+
};
807+
731808
static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
732809
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
733810
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
@@ -3132,6 +3209,31 @@ static const struct qmp_phy_cfg ipq9574_gen3x2_pciephy_cfg = {
31323209
.pipe_clock_rate = 250000000,
31333210
};
31343211

3212+
static const struct qmp_phy_cfg qcs615_pciephy_cfg = {
3213+
.lanes = 1,
3214+
3215+
.offsets = &qmp_pcie_offsets_v2,
3216+
3217+
.tbls = {
3218+
.serdes = qcs615_pcie_serdes_tbl,
3219+
.serdes_num = ARRAY_SIZE(qcs615_pcie_serdes_tbl),
3220+
.tx = qcs615_pcie_tx_tbl,
3221+
.tx_num = ARRAY_SIZE(qcs615_pcie_tx_tbl),
3222+
.rx = qcs615_pcie_rx_tbl,
3223+
.rx_num = ARRAY_SIZE(qcs615_pcie_rx_tbl),
3224+
.pcs = qcs615_pcie_pcs_tbl,
3225+
.pcs_num = ARRAY_SIZE(qcs615_pcie_pcs_tbl),
3226+
},
3227+
.reset_list = sdm845_pciephy_reset_l,
3228+
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3229+
.vreg_list = qmp_phy_vreg_l,
3230+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3231+
.regs = pciephy_v2_regs_layout,
3232+
3233+
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3234+
.phy_status = PHYSTATUS,
3235+
};
3236+
31353237
static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
31363238
.lanes = 1,
31373239

@@ -4611,6 +4713,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
46114713
}, {
46124714
.compatible = "qcom,msm8998-qmp-pcie-phy",
46134715
.data = &msm8998_pciephy_cfg,
4716+
}, {
4717+
.compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy",
4718+
.data = &qcs615_pciephy_cfg,
46144719
}, {
46154720
.compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy",
46164721
.data = &sa8775p_qmp_gen4x2_pciephy_cfg,

‎drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@
3434
#define QPHY_V2_PCS_USB_PCS_STATUS 0x17c /* USB */
3535
#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8
3636
#define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac
37+
#define QPHY_V2_PCS_SIGDET_CNTRL 0x1b0
3738
#define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8
3839
#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
3940
#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0

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