Skip to content

Commit 217e677

Browse files
wkarnyrafaeljw
authored andcommitted
cpufreq: amd-pstate: Write CPPC enable bit per-socket
Currently amd_pstate sets CPPC enable bit in MSR_AMD_CPPC_ENABLE only for the CPU where the module_init happened. But MSR_AMD_CPPC_ENABLE is per-socket. This causes CPPC enable bit to set for only one socket for servers with more than one physical packages. To fix this write MSR_AMD_CPPC_ENABLE per-socket. Also, handle duplicate calls for cppc_enable, because it's called from per-policy/per-core callbacks and can result in duplicate MSR writes. Before the fix: amd@amd:~$ sudo rdmsr -a 0xc00102b1 | uniq --count 192 0 192 1 After the fix: amd@amd:~$ sudo rdmsr -a 0xc00102b1 | uniq --count 384 1 Suggested-by: Gautham R. Shenoy <[email protected]> Signed-off-by: Wyes Karny <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Rafael J. Wysocki <[email protected]>
1 parent b4a11fa commit 217e677

File tree

1 file changed

+27
-1
lines changed

1 file changed

+27
-1
lines changed

drivers/cpufreq/amd-pstate.c

Lines changed: 27 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,7 @@ static struct cpufreq_driver *current_pstate_driver;
6363
static struct cpufreq_driver amd_pstate_driver;
6464
static struct cpufreq_driver amd_pstate_epp_driver;
6565
static int cppc_state = AMD_PSTATE_DISABLE;
66+
static bool cppc_enabled;
6667

6768
/*
6869
* AMD Energy Preference Performance (EPP)
@@ -228,14 +229,38 @@ static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata,
228229

229230
static inline int pstate_enable(bool enable)
230231
{
231-
return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable);
232+
int ret, cpu;
233+
unsigned long logical_proc_id_mask = 0;
234+
235+
if (enable == cppc_enabled)
236+
return 0;
237+
238+
for_each_present_cpu(cpu) {
239+
unsigned long logical_id = topology_logical_die_id(cpu);
240+
241+
if (test_bit(logical_id, &logical_proc_id_mask))
242+
continue;
243+
244+
set_bit(logical_id, &logical_proc_id_mask);
245+
246+
ret = wrmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_ENABLE,
247+
enable);
248+
if (ret)
249+
return ret;
250+
}
251+
252+
cppc_enabled = enable;
253+
return 0;
232254
}
233255

234256
static int cppc_enable(bool enable)
235257
{
236258
int cpu, ret = 0;
237259
struct cppc_perf_ctrls perf_ctrls;
238260

261+
if (enable == cppc_enabled)
262+
return 0;
263+
239264
for_each_present_cpu(cpu) {
240265
ret = cppc_set_enable(cpu, enable);
241266
if (ret)
@@ -251,6 +276,7 @@ static int cppc_enable(bool enable)
251276
}
252277
}
253278

279+
cppc_enabled = enable;
254280
return ret;
255281
}
256282

0 commit comments

Comments
 (0)