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ziswilerLorenzo Pieralisi
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PCI: tegra: Fix afi_pex2_ctrl reg offset for Tegra30
Fix AFI_PEX2_CTRL reg offset for Tegra30 by moving it from the Tegra20 SoC struct where it erroneously got added. This fixes the AFI_PEX2_CTRL reg offset being uninitialised subsequently failing to bring up the third PCIe port. Fixes: adb2653 ("PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of SoC struct") Signed-off-by: Marcel Ziswiler <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]> Acked-by: Thierry Reding <[email protected]>
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drivers/pci/controller/pci-tegra.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2499,7 +2499,6 @@ static const struct tegra_pcie_soc tegra20_pcie = {
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.num_ports = 2,
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.ports = tegra20_pcie_ports,
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.msi_base_shift = 0,
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.afi_pex2_ctrl = 0x128,
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.pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
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.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
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.pads_refclk_cfg0 = 0xfa5cfa5c,
@@ -2528,6 +2527,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
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.num_ports = 3,
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.ports = tegra30_pcie_ports,
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.msi_base_shift = 8,
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.afi_pex2_ctrl = 0x128,
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.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
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.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
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.pads_refclk_cfg0 = 0xfa5cfa5c,

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