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torvaldstorvalds
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Merge tag 'drm-next-2020-04-10' of git://anongit.freedesktop.org/drm/drm
Pull more drm fixes from Dave Airlie: "As expected, more fixes did turn up in the latter part of the week. The drm_local_map build regression fix is here, along with temporary disabling of the hugepage work due to some amdgpu related crashes. Otherwise it's just a bunch of i915, and amdgpu fixes. legacy: - fix drm_local_map.offset type ttm: - temporarily disable hugepages to debug amdgpu problems. prime: - fix sg extraction amdgpu: - Various Renoir fixes - Fix gfx clockgating sequence on gfx10 - RAS fixes - Avoid MST property creation after registration - Various cursor/viewport fixes - Fix a confusing log message about optional firmwares i915: - Flush all the reloc_gpu batch (Chris) - Ignore readonly failures when updating relocs (Chris) - Fill all the unused space in the GGTT (Chris) - Return the right vswing table (Jose) - Don't enable DDI IO power on a TypeC port in TBT mode for ICL+ (Imre) analogix_dp: - probe fix virtio: - oob fix in object create" * tag 'drm-next-2020-04-10' of git://anongit.freedesktop.org/drm/drm: (34 commits) drm/ttm: Temporarily disable the huge_fault() callback drm/bridge: analogix_dp: Split bind() into probe() and real bind() drm/legacy: Fix type for drm_local_map.offset drm/amdgpu/display: fix warning when compiling without debugfs drm/amdgpu: unify fw_write_wait for new gfx9 asics drm/amd/powerplay: error out on forcing clock setting not supported drm/amdgpu: fix gfx hang during suspend with video playback (v2) drm/amd/display: Check for null fclk voltage when parsing clock table drm/amd/display: Acknowledge wm_optimized_required drm/amd/display: Make cursor source translation adjustment optional drm/amd/display: Calculate scaling ratios on every medium/full update drm/amd/display: Program viewport when source pos changes for DCN20 hw seq drm/amd/display: Fix incorrect cursor pos on scaled primary plane drm/amd/display: change default pipe_split policy for DCN1 drm/amd/display: Translate cursor position by source rect drm/amd/display: Update stream adjust in dc_stream_adjust_vmin_vmax drm/amd/display: Avoid create MST prop after registration drm/amdgpu/psp: dont warn on missing optional TA's drm/amdgpu: update RAS related dmesg print drm/amdgpu: resolve mGPU RAS query instability ...
2 parents 4aafdf6 + 74bd4f0 commit 21c5b3c

33 files changed

+354
-192
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2340,8 +2340,6 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
23402340
{
23412341
int i, r;
23422342

2343-
amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2344-
amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
23452343

23462344
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
23472345
if (!adev->ip_blocks[i].status.valid)
@@ -3356,6 +3354,9 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
33563354
}
33573355
}
33583356

3357+
amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
3358+
amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
3359+
33593360
amdgpu_amdkfd_suspend(adev, !fbcon);
33603361

33613362
amdgpu_ras_suspend(adev);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -89,7 +89,8 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
8989
adev->pm.ac_power = true;
9090
else
9191
adev->pm.ac_power = false;
92-
if (adev->powerplay.pp_funcs->enable_bapm)
92+
if (adev->powerplay.pp_funcs &&
93+
adev->powerplay.pp_funcs->enable_bapm)
9394
amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
9495
mutex_unlock(&adev->pm.mutex);
9596

‎drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -818,7 +818,7 @@ static int psp_ras_initialize(struct psp_context *psp)
818818

819819
if (!psp->adev->psp.ta_ras_ucode_size ||
820820
!psp->adev->psp.ta_ras_start_addr) {
821-
dev_warn(psp->adev->dev, "RAS: ras ta ucode is not available\n");
821+
dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n");
822822
return 0;
823823
}
824824

@@ -902,7 +902,7 @@ static int psp_hdcp_initialize(struct psp_context *psp)
902902

903903
if (!psp->adev->psp.ta_hdcp_ucode_size ||
904904
!psp->adev->psp.ta_hdcp_start_addr) {
905-
dev_warn(psp->adev->dev, "HDCP: hdcp ta ucode is not available\n");
905+
dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
906906
return 0;
907907
}
908908

@@ -1048,7 +1048,7 @@ static int psp_dtm_initialize(struct psp_context *psp)
10481048

10491049
if (!psp->adev->psp.ta_dtm_ucode_size ||
10501050
!psp->adev->psp.ta_dtm_start_addr) {
1051-
dev_warn(psp->adev->dev, "DTM: dtm ta ucode is not available\n");
1051+
dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
10521052
return 0;
10531053
}
10541054

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

Lines changed: 15 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1424,12 +1424,22 @@ static void amdgpu_ras_do_recovery(struct work_struct *work)
14241424
{
14251425
struct amdgpu_ras *ras =
14261426
container_of(work, struct amdgpu_ras, recovery_work);
1427+
struct amdgpu_device *remote_adev = NULL;
1428+
struct amdgpu_device *adev = ras->adev;
1429+
struct list_head device_list, *device_list_handle = NULL;
1430+
struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, false);
1431+
1432+
/* Build list of devices to query RAS related errors */
1433+
if (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
1434+
device_list_handle = &hive->device_list;
1435+
} else {
1436+
list_add_tail(&adev->gmc.xgmi.head, &device_list);
1437+
device_list_handle = &device_list;
1438+
}
14271439

1428-
/*
1429-
* Query and print non zero error counter per IP block for
1430-
* awareness before recovering GPU.
1431-
*/
1432-
amdgpu_ras_log_on_err_counter(ras->adev);
1440+
list_for_each_entry(remote_adev, device_list_handle, gmc.xgmi.head) {
1441+
amdgpu_ras_log_on_err_counter(remote_adev);
1442+
}
14331443

14341444
if (amdgpu_device_should_recover_gpu(ras->adev))
14351445
amdgpu_device_gpu_recover(ras->adev, 0);

‎drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

Lines changed: 16 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -279,7 +279,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
279279

280280
#define DEFAULT_SH_MEM_CONFIG \
281281
((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
282-
(SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
282+
(SH_MEM_ALIGNMENT_MODE_DWORD << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
283283
(SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
284284
(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
285285

@@ -4104,6 +4104,12 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade
41044104

41054105
/* It is disabled by HW by default */
41064106
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
4107+
/* 0 - Disable some blocks' MGCG */
4108+
WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
4109+
WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
4110+
WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
4111+
WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
4112+
41074113
/* 1 - RLC_CGTT_MGCG_OVERRIDE */
41084114
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
41094115
data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
@@ -4143,19 +4149,20 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade
41434149
if (def != data)
41444150
WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
41454151

4146-
/* 2 - disable MGLS in RLC */
4152+
/* 2 - disable MGLS in CP */
4153+
data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4154+
if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
4155+
data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4156+
WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4157+
}
4158+
4159+
/* 3 - disable MGLS in RLC */
41474160
data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
41484161
if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
41494162
data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
41504163
WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
41514164
}
41524165

4153-
/* 3 - disable MGLS in CP */
4154-
data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4155-
if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
4156-
data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4157-
WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4158-
}
41594166
}
41604167
}
41614168

@@ -4266,7 +4273,7 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
42664273
/* === CGCG /CGLS for GFX 3D Only === */
42674274
gfx_v10_0_update_3d_clock_gating(adev, enable);
42684275
/* === MGCG + MGLS === */
4269-
gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
4276+
/* gfx_v10_0_update_medium_grain_clock_gating(adev, enable); */
42704277
}
42714278

42724279
if (adev->cg_flags &

‎drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1217,6 +1217,8 @@ static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
12171217
adev->gfx.mec_fw_write_wait = true;
12181218
break;
12191219
default:
1220+
adev->gfx.me_fw_write_wait = true;
1221+
adev->gfx.mec_fw_write_wait = true;
12201222
break;
12211223
}
12221224
}

‎drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -710,14 +710,16 @@ static int gfx_v9_4_query_utc_edc_status(struct amdgpu_device *adev,
710710

711711
sec_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, SEC_COUNT);
712712
if (sec_count) {
713-
DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
713+
dev_info(adev->dev,
714+
"Instance[%d]: SubBlock %s, SEC %d\n", i,
714715
vml2_mems[i], sec_count);
715716
err_data->ce_count += sec_count;
716717
}
717718

718719
ded_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, DED_COUNT);
719720
if (ded_count) {
720-
DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,
721+
dev_info(adev->dev,
722+
"Instance[%d]: SubBlock %s, DED %d\n", i,
721723
vml2_mems[i], ded_count);
722724
err_data->ue_count += ded_count;
723725
}

‎drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1539,8 +1539,11 @@ static const struct soc15_reg_entry mmhub_v9_4_edc_cnt_regs[] = {
15391539
{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 0, 0, 0 },
15401540
};
15411541

1542-
static int mmhub_v9_4_get_ras_error_count(const struct soc15_reg_entry *reg,
1543-
uint32_t value, uint32_t *sec_count, uint32_t *ded_count)
1542+
static int mmhub_v9_4_get_ras_error_count(struct amdgpu_device *adev,
1543+
const struct soc15_reg_entry *reg,
1544+
uint32_t value,
1545+
uint32_t *sec_count,
1546+
uint32_t *ded_count)
15441547
{
15451548
uint32_t i;
15461549
uint32_t sec_cnt, ded_cnt;
@@ -1553,7 +1556,7 @@ static int mmhub_v9_4_get_ras_error_count(const struct soc15_reg_entry *reg,
15531556
mmhub_v9_4_ras_fields[i].sec_count_mask) >>
15541557
mmhub_v9_4_ras_fields[i].sec_count_shift;
15551558
if (sec_cnt) {
1556-
DRM_INFO("MMHUB SubBlock %s, SEC %d\n",
1559+
dev_info(adev->dev, "MMHUB SubBlock %s, SEC %d\n",
15571560
mmhub_v9_4_ras_fields[i].name,
15581561
sec_cnt);
15591562
*sec_count += sec_cnt;
@@ -1563,7 +1566,7 @@ static int mmhub_v9_4_get_ras_error_count(const struct soc15_reg_entry *reg,
15631566
mmhub_v9_4_ras_fields[i].ded_count_mask) >>
15641567
mmhub_v9_4_ras_fields[i].ded_count_shift;
15651568
if (ded_cnt) {
1566-
DRM_INFO("MMHUB SubBlock %s, DED %d\n",
1569+
dev_info(adev->dev, "MMHUB SubBlock %s, DED %d\n",
15671570
mmhub_v9_4_ras_fields[i].name,
15681571
ded_cnt);
15691572
*ded_count += ded_cnt;
@@ -1588,7 +1591,7 @@ static void mmhub_v9_4_query_ras_error_count(struct amdgpu_device *adev,
15881591
reg_value =
15891592
RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i]));
15901593
if (reg_value)
1591-
mmhub_v9_4_get_ras_error_count(&mmhub_v9_4_edc_cnt_regs[i],
1594+
mmhub_v9_4_get_ras_error_count(adev, &mmhub_v9_4_edc_cnt_regs[i],
15921595
reg_value, &sec_count, &ded_count);
15931596
}
15941597

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

Lines changed: 7 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -4723,10 +4723,10 @@ amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
47234723
static int
47244724
amdgpu_dm_connector_late_register(struct drm_connector *connector)
47254725
{
4726+
#if defined(CONFIG_DEBUG_FS)
47264727
struct amdgpu_dm_connector *amdgpu_dm_connector =
47274728
to_amdgpu_dm_connector(connector);
47284729

4729-
#if defined(CONFIG_DEBUG_FS)
47304730
connector_debugfs_init(amdgpu_dm_connector);
47314731
#endif
47324732

@@ -5929,7 +5929,8 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
59295929
adev->mode_info.underscan_vborder_property,
59305930
0);
59315931

5932-
drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
5932+
if (!aconnector->mst_port)
5933+
drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
59335934

59345935
/* This defaults to the max in the range, but we want 8bpc for non-edp. */
59355936
aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP) ? 16 : 8;
@@ -5948,8 +5949,9 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
59485949
&aconnector->base.base,
59495950
dm->ddev->mode_config.hdr_output_metadata_property, 0);
59505951

5951-
drm_connector_attach_vrr_capable_property(
5952-
&aconnector->base);
5952+
if (!aconnector->mst_port)
5953+
drm_connector_attach_vrr_capable_property(&aconnector->base);
5954+
59535955
#ifdef CONFIG_DRM_AMD_DC_HDCP
59545956
if (adev->dm.hdcp_workqueue)
59555957
drm_connector_attach_content_protection_property(&aconnector->base, true);
@@ -6272,12 +6274,6 @@ static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
62726274
y <= -amdgpu_crtc->max_cursor_height)
62736275
return 0;
62746276

6275-
if (crtc->primary->state) {
6276-
/* avivo cursor are offset into the total surface */
6277-
x += crtc->primary->state->src_x >> 16;
6278-
y += crtc->primary->state->src_y >> 16;
6279-
}
6280-
62816277
if (x < 0) {
62826278
xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
62836279
x = 0;
@@ -6287,6 +6283,7 @@ static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
62876283
y = 0;
62886284
}
62896285
position->enable = true;
6286+
position->translate_by_source = true;
62906287
position->x = x;
62916288
position->y = y;
62926289
position->x_hotspot = xorigin;

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -410,6 +410,14 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
410410
drm_connector_attach_encoder(&aconnector->base,
411411
&aconnector->mst_encoder->base);
412412

413+
connector->max_bpc_property = master->base.max_bpc_property;
414+
if (connector->max_bpc_property)
415+
drm_connector_attach_max_bpc_property(connector, 8, 16);
416+
417+
connector->vrr_capable_property = master->base.vrr_capable_property;
418+
if (connector->vrr_capable_property)
419+
drm_connector_attach_vrr_capable_property(connector);
420+
413421
drm_object_attach_property(
414422
&connector->base,
415423
dev->mode_config.path_property,

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