Skip to content

Commit 22565ae

Browse files
torvaldstorvalds
committed
Merge tag 'drm-fixes-2022-09-23-1' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie: "Regular fixes for the week, i915, mediatek, hisilicon, mgag200 and panel have some small fixes. amdgpu has more stack size fixes for clang build, and fixes for new IPs, but all with low regression chances since they are for stuff new in v6.0. i915: - avoid a general protection failure when using perf/OA - avoid kernel warnings on driver release amdgpu: - SDMA 6.x fix - GPUVM TF fix - DCN 3.2.x fixes - DCN 3.1.x fixes - SMU 13.x fixes - Clang stack size fixes for recently enabled DML code - Fix drm dirty callback change on non-atomic cases - USB4 display fix mediatek: - dsi: Add atomic {destroy,duplicate}_state, reset callbacks - dsi: Move mtk_dsi_stop() call back to mtk_dsi_poweroff() - Fix wrong dither settings hisilicon: - Depend on MMU mgag200: - Fix console on G200ER panel: - Fix innolux_g121i1_l01 bus format" * tag 'drm-fixes-2022-09-23-1' of git://anongit.freedesktop.org/drm/drm: (30 commits) MAINTAINERS: switch graphics to airlied other addresses drm/mediatek: dsi: Move mtk_dsi_stop() call back to mtk_dsi_poweroff() drm/amd/display: Reduce number of arguments of dml314's CalculateFlipSchedule() drm/amd/display: Reduce number of arguments of dml314's CalculateWatermarksAndDRAMSpeedChangeSupport() drm/amdgpu: don't register a dirty callback for non-atomic drm/amd/pm: drop the pptable related workarounds for SMU 13.0.0 drm/amd/pm: add support for 3794 pptable for SMU13.0.0 drm/amd/display: correct num_dsc based on HW cap drm/amd/display: Disable OTG WA for the plane_state NULL case on DCN314 drm/amd/display: Add shift and mask for ICH_RESET_AT_END_OF_LINE drm/amd/display: increase dcn315 pstate change latency drm/amd/display: Fix DP MST timeslot issue when fallback happened drm/amd/display: Display distortion after hotplug 5K tiled display drm/amd/display: Update dummy P-state search to use DCN32 DML drm/amd/display: skip audio setup when audio stream is enabled drm/amd/display: update gamut remap if plane has changed drm/amd/display: Assume an LTTPR is always present on fixed_vs links drm/amd/display: fix dcn315 memory channel count and width read drm/amd/display: Fix double cursor on non-video RGB MPO drm/amd/display: Only consider pixle rate div policy for DCN32+ ...
2 parents bf68294 + 8288206 commit 22565ae

36 files changed

+340
-720
lines changed

‎MAINTAINERS

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -671,7 +671,8 @@ F: fs/afs/
671671
F: include/trace/events/afs.h
672672

673673
AGPGART DRIVER
674-
M: David Airlie <[email protected]>
674+
M: David Airlie <[email protected]>
675+
L: [email protected]
675676
S: Maintained
676677
T: git git://anongit.freedesktop.org/drm/drm
677678
F: drivers/char/agp/
@@ -6753,7 +6754,7 @@ F: Documentation/devicetree/bindings/display/panel/samsung,lms380kf01.yaml
67536754
F: drivers/gpu/drm/panel/panel-widechips-ws2401.c
67546755

67556756
DRM DRIVERS
6756-
M: David Airlie <airlied@linux.ie>
6757+
M: David Airlie <airlied@gmail.com>
67576758
M: Daniel Vetter <[email protected]>
67586759
L: [email protected]
67596760
S: Maintained
@@ -21567,7 +21568,7 @@ F: drivers/gpio/gpio-virtio.c
2156721568
F: include/uapi/linux/virtio_gpio.h
2156821569

2156921570
VIRTIO GPU DRIVER
21570-
M: David Airlie <airlied@linux.ie>
21571+
M: David Airlie <airlied@redhat.com>
2157121572
M: Gerd Hoffmann <[email protected]>
2157221573
R: Gurchetan Singh <[email protected]>
2157321574
R: Chia-I Wu <[email protected]>

‎drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@
3939
#include <linux/pm_runtime.h>
4040
#include <drm/drm_crtc_helper.h>
4141
#include <drm/drm_damage_helper.h>
42+
#include <drm/drm_drv.h>
4243
#include <drm/drm_edid.h>
4344
#include <drm/drm_gem_framebuffer_helper.h>
4445
#include <drm/drm_fb_helper.h>
@@ -497,6 +498,11 @@ bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
497498
static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
498499
.destroy = drm_gem_fb_destroy,
499500
.create_handle = drm_gem_fb_create_handle,
501+
};
502+
503+
static const struct drm_framebuffer_funcs amdgpu_fb_funcs_atomic = {
504+
.destroy = drm_gem_fb_destroy,
505+
.create_handle = drm_gem_fb_create_handle,
500506
.dirty = drm_atomic_helper_dirtyfb,
501507
};
502508

@@ -1102,7 +1108,10 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev,
11021108
if (ret)
11031109
goto err;
11041110

1105-
ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
1111+
if (drm_drv_uses_atomic_modeset(dev))
1112+
ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs_atomic);
1113+
else
1114+
ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
11061115
if (ret)
11071116
goto err;
11081117

‎drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -181,6 +181,9 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
181181
for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) {
182182
if (adev->ip_versions[SDMA0_HWIP][0] < IP_VERSION(6, 0, 0))
183183
adev->mes.sdma_hqd_mask[i] = i ? 0 : 0x3fc;
184+
/* zero sdma_hqd_mask for non-existent engine */
185+
else if (adev->sdma.num_instances == 1)
186+
adev->mes.sdma_hqd_mask[i] = i ? 0 : 0xfc;
184187
else
185188
adev->mes.sdma_hqd_mask[i] = 0xfc;
186189
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2484,8 +2484,7 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
24842484
/* Intentionally setting invalid PTE flag
24852485
* combination to force a no-retry-fault
24862486
*/
2487-
flags = AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE |
2488-
AMDGPU_PTE_TF;
2487+
flags = AMDGPU_PTE_SNOOPED | AMDGPU_PTE_PRT;
24892488
value = 0;
24902489
} else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
24912490
/* Redirect the access to the dummy page */

‎drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1103,10 +1103,13 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
11031103
*flags |= AMDGPU_PDE_BFS(0x9);
11041104

11051105
} else if (level == AMDGPU_VM_PDB0) {
1106-
if (*flags & AMDGPU_PDE_PTE)
1106+
if (*flags & AMDGPU_PDE_PTE) {
11071107
*flags &= ~AMDGPU_PDE_PTE;
1108-
else
1108+
if (!(*flags & AMDGPU_PTE_VALID))
1109+
*addr |= 1 << PAGE_SHIFT;
1110+
} else {
11091111
*flags |= AMDGPU_PTE_TF;
1112+
}
11101113
}
11111114
}
11121115

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4759,7 +4759,7 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
47594759
plane_info->visible = true;
47604760
plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
47614761

4762-
plane_info->layer_index = 0;
4762+
plane_info->layer_index = plane_state->normalized_zpos;
47634763

47644764
ret = fill_plane_color_attributes(plane_state, plane_info->format,
47654765
&plane_info->color_space);
@@ -4827,7 +4827,7 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,
48274827
dc_plane_state->global_alpha = plane_info.global_alpha;
48284828
dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
48294829
dc_plane_state->dcc = plane_info.dcc;
4830-
dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0
4830+
dc_plane_state->layer_index = plane_info.layer_index;
48314831
dc_plane_state->flip_int_enabled = true;
48324832

48334833
/*
@@ -9485,6 +9485,14 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
94859485
}
94869486
}
94879487

9488+
/*
9489+
* DC consults the zpos (layer_index in DC terminology) to determine the
9490+
* hw plane on which to enable the hw cursor (see
9491+
* `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
9492+
* atomic state, so call drm helper to normalize zpos.
9493+
*/
9494+
drm_atomic_normalize_zpos(dev, state);
9495+
94889496
/* Remove exiting planes if they are modified */
94899497
for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
94909498
ret = dm_update_plane_state(dc, state, plane,

‎drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -99,7 +99,7 @@ static int dcn31_get_active_display_cnt_wa(
9999
return display_count;
100100
}
101101

102-
static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
102+
static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
103103
{
104104
struct dc *dc = clk_mgr_base->ctx->dc;
105105
int i;
@@ -110,9 +110,10 @@ static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
110110
if (pipe->top_pipe || pipe->prev_odm_pipe)
111111
continue;
112112
if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
113-
if (disable)
113+
if (disable) {
114114
pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
115-
else
115+
reset_sync_context_for_pipe(dc, context, i);
116+
} else
116117
pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
117118
}
118119
}
@@ -211,11 +212,11 @@ void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
211212
}
212213

213214
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
214-
dcn31_disable_otg_wa(clk_mgr_base, true);
215+
dcn31_disable_otg_wa(clk_mgr_base, context, true);
215216

216217
clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
217218
dcn31_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
218-
dcn31_disable_otg_wa(clk_mgr_base, false);
219+
dcn31_disable_otg_wa(clk_mgr_base, context, false);
219220

220221
update_dispclk = true;
221222
}

‎drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -119,7 +119,7 @@ static int dcn314_get_active_display_cnt_wa(
119119
return display_count;
120120
}
121121

122-
static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
122+
static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
123123
{
124124
struct dc *dc = clk_mgr_base->ctx->dc;
125125
int i;
@@ -129,11 +129,11 @@ static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
129129

130130
if (pipe->top_pipe || pipe->prev_odm_pipe)
131131
continue;
132-
if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||
133-
dc_is_virtual_signal(pipe->stream->signal))) {
134-
if (disable)
132+
if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
133+
if (disable) {
135134
pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
136-
else
135+
reset_sync_context_for_pipe(dc, context, i);
136+
} else
137137
pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
138138
}
139139
}
@@ -233,11 +233,11 @@ void dcn314_update_clocks(struct clk_mgr *clk_mgr_base,
233233
}
234234

235235
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
236-
dcn314_disable_otg_wa(clk_mgr_base, true);
236+
dcn314_disable_otg_wa(clk_mgr_base, context, true);
237237

238238
clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
239239
dcn314_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
240-
dcn314_disable_otg_wa(clk_mgr_base, false);
240+
dcn314_disable_otg_wa(clk_mgr_base, context, false);
241241

242242
update_dispclk = true;
243243
}

‎drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

Lines changed: 21 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,9 @@
4646
#define TO_CLK_MGR_DCN315(clk_mgr)\
4747
container_of(clk_mgr, struct clk_mgr_dcn315, base)
4848

49+
#define UNSUPPORTED_DCFCLK 10000000
50+
#define MIN_DPP_DISP_CLK 100000
51+
4952
static int dcn315_get_active_display_cnt_wa(
5053
struct dc *dc,
5154
struct dc_state *context)
@@ -79,7 +82,7 @@ static int dcn315_get_active_display_cnt_wa(
7982
return display_count;
8083
}
8184

82-
static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
85+
static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
8386
{
8487
struct dc *dc = clk_mgr_base->ctx->dc;
8588
int i;
@@ -91,9 +94,10 @@ static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
9194
continue;
9295
if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||
9396
dc_is_virtual_signal(pipe->stream->signal))) {
94-
if (disable)
97+
if (disable) {
9598
pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
96-
else
99+
reset_sync_context_for_pipe(dc, context, i);
100+
} else
97101
pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
98102
}
99103
}
@@ -146,6 +150,9 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
146150
}
147151
}
148152

153+
/* Lock pstate by requesting unsupported dcfclk if change is unsupported */
154+
if (!new_clocks->p_state_change_support)
155+
new_clocks->dcfclk_khz = UNSUPPORTED_DCFCLK;
149156
if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
150157
clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
151158
dcn315_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
@@ -159,10 +166,10 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
159166

160167
// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
161168
if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
162-
if (new_clocks->dppclk_khz < 100000)
163-
new_clocks->dppclk_khz = 100000;
164-
if (new_clocks->dispclk_khz < 100000)
165-
new_clocks->dispclk_khz = 100000;
169+
if (new_clocks->dppclk_khz < MIN_DPP_DISP_CLK)
170+
new_clocks->dppclk_khz = MIN_DPP_DISP_CLK;
171+
if (new_clocks->dispclk_khz < MIN_DPP_DISP_CLK)
172+
new_clocks->dispclk_khz = MIN_DPP_DISP_CLK;
166173
}
167174

168175
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
@@ -175,12 +182,12 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
175182
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
176183
/* No need to apply the w/a if we haven't taken over from bios yet */
177184
if (clk_mgr_base->clks.dispclk_khz)
178-
dcn315_disable_otg_wa(clk_mgr_base, true);
185+
dcn315_disable_otg_wa(clk_mgr_base, context, true);
179186

180187
clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
181188
dcn315_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
182189
if (clk_mgr_base->clks.dispclk_khz)
183-
dcn315_disable_otg_wa(clk_mgr_base, false);
190+
dcn315_disable_otg_wa(clk_mgr_base, context, false);
184191

185192
update_dispclk = true;
186193
}
@@ -275,31 +282,31 @@ static struct wm_table ddr5_wm_table = {
275282
{
276283
.wm_inst = WM_A,
277284
.wm_type = WM_TYPE_PSTATE_CHG,
278-
.pstate_latency_us = 64.0,
285+
.pstate_latency_us = 129.0,
279286
.sr_exit_time_us = 11.5,
280287
.sr_enter_plus_exit_time_us = 14.5,
281288
.valid = true,
282289
},
283290
{
284291
.wm_inst = WM_B,
285292
.wm_type = WM_TYPE_PSTATE_CHG,
286-
.pstate_latency_us = 64.0,
293+
.pstate_latency_us = 129.0,
287294
.sr_exit_time_us = 11.5,
288295
.sr_enter_plus_exit_time_us = 14.5,
289296
.valid = true,
290297
},
291298
{
292299
.wm_inst = WM_C,
293300
.wm_type = WM_TYPE_PSTATE_CHG,
294-
.pstate_latency_us = 64.0,
301+
.pstate_latency_us = 129.0,
295302
.sr_exit_time_us = 11.5,
296303
.sr_enter_plus_exit_time_us = 14.5,
297304
.valid = true,
298305
},
299306
{
300307
.wm_inst = WM_D,
301308
.wm_type = WM_TYPE_PSTATE_CHG,
302-
.pstate_latency_us = 64.0,
309+
.pstate_latency_us = 129.0,
303310
.sr_exit_time_us = 11.5,
304311
.sr_enter_plus_exit_time_us = 14.5,
305312
.valid = true,
@@ -556,8 +563,7 @@ static void dcn315_clk_mgr_helper_populate_bw_params(
556563
ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
557564
bw_params->vram_type = bios_info->memory_type;
558565
bw_params->num_channels = bios_info->ma_channel_number;
559-
if (!bw_params->num_channels)
560-
bw_params->num_channels = 2;
566+
bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
561567

562568
for (i = 0; i < WM_SET_COUNT; i++) {
563569
bw_params->wm_table.entries[i].wm_inst = i;

‎drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,7 @@ static int dcn316_get_active_display_cnt_wa(
112112
return display_count;
113113
}
114114

115-
static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
115+
static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
116116
{
117117
struct dc *dc = clk_mgr_base->ctx->dc;
118118
int i;
@@ -124,9 +124,10 @@ static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
124124
continue;
125125
if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||
126126
dc_is_virtual_signal(pipe->stream->signal))) {
127-
if (disable)
127+
if (disable) {
128128
pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
129-
else
129+
reset_sync_context_for_pipe(dc, context, i);
130+
} else
130131
pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
131132
}
132133
}
@@ -221,11 +222,11 @@ static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base,
221222
}
222223

223224
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
224-
dcn316_disable_otg_wa(clk_mgr_base, true);
225+
dcn316_disable_otg_wa(clk_mgr_base, context, true);
225226

226227
clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
227228
dcn316_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
228-
dcn316_disable_otg_wa(clk_mgr_base, false);
229+
dcn316_disable_otg_wa(clk_mgr_base, context, false);
229230

230231
update_dispclk = true;
231232
}

0 commit comments

Comments
 (0)