|
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8350.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: Qualcomm SM8350 PCI Express Root Complex |
| 8 | + |
| 9 | +maintainers: |
| 10 | + - Bjorn Andersson <[email protected]> |
| 11 | + - Manivannan Sadhasivam <[email protected]> |
| 12 | + |
| 13 | +description: |
| 14 | + Qualcomm SM8350 SoC PCIe root complex controller is based on the Synopsys |
| 15 | + DesignWare PCIe IP. |
| 16 | + |
| 17 | +properties: |
| 18 | + compatible: |
| 19 | + const: qcom,pcie-sm8350 |
| 20 | + |
| 21 | + reg: |
| 22 | + minItems: 5 |
| 23 | + maxItems: 6 |
| 24 | + |
| 25 | + reg-names: |
| 26 | + minItems: 5 |
| 27 | + items: |
| 28 | + - const: parf # Qualcomm specific registers |
| 29 | + - const: dbi # DesignWare PCIe registers |
| 30 | + - const: elbi # External local bus interface registers |
| 31 | + - const: atu # ATU address space |
| 32 | + - const: config # PCIe configuration space |
| 33 | + - const: mhi # MHI registers |
| 34 | + |
| 35 | + clocks: |
| 36 | + minItems: 8 |
| 37 | + maxItems: 9 |
| 38 | + |
| 39 | + clock-names: |
| 40 | + minItems: 8 |
| 41 | + items: |
| 42 | + - const: aux # Auxiliary clock |
| 43 | + - const: cfg # Configuration clock |
| 44 | + - const: bus_master # Master AXI clock |
| 45 | + - const: bus_slave # Slave AXI clock |
| 46 | + - const: slave_q2a # Slave Q2A clock |
| 47 | + - const: tbu # PCIe TBU clock |
| 48 | + - const: ddrss_sf_tbu # PCIe SF TBU clock |
| 49 | + - const: aggre1 # Aggre NoC PCIe1 AXI clock |
| 50 | + - const: aggre0 # Aggre NoC PCIe0 AXI clock |
| 51 | + |
| 52 | + interrupts: |
| 53 | + minItems: 8 |
| 54 | + maxItems: 8 |
| 55 | + |
| 56 | + interrupt-names: |
| 57 | + items: |
| 58 | + - const: msi0 |
| 59 | + - const: msi1 |
| 60 | + - const: msi2 |
| 61 | + - const: msi3 |
| 62 | + - const: msi4 |
| 63 | + - const: msi5 |
| 64 | + - const: msi6 |
| 65 | + - const: msi7 |
| 66 | + |
| 67 | + resets: |
| 68 | + maxItems: 1 |
| 69 | + |
| 70 | + reset-names: |
| 71 | + items: |
| 72 | + - const: pci |
| 73 | + |
| 74 | +oneOf: |
| 75 | + - properties: |
| 76 | + interrupts: |
| 77 | + maxItems: 1 |
| 78 | + interrupt-names: |
| 79 | + items: |
| 80 | + - const: msi |
| 81 | + |
| 82 | + - properties: |
| 83 | + interrupts: |
| 84 | + minItems: 8 |
| 85 | + interrupt-names: |
| 86 | + items: |
| 87 | + - const: msi0 |
| 88 | + - const: msi1 |
| 89 | + - const: msi2 |
| 90 | + - const: msi3 |
| 91 | + - const: msi4 |
| 92 | + - const: msi5 |
| 93 | + - const: msi6 |
| 94 | + - const: msi7 |
| 95 | + |
| 96 | +allOf: |
| 97 | + - $ref: qcom,pcie-common.yaml# |
| 98 | + |
| 99 | +unevaluatedProperties: false |
| 100 | + |
| 101 | +examples: |
| 102 | + - | |
| 103 | + #include <dt-bindings/clock/qcom,gcc-sm8350.h> |
| 104 | + #include <dt-bindings/gpio/gpio.h> |
| 105 | + #include <dt-bindings/interconnect/qcom,sm8350.h> |
| 106 | + #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 107 | +
|
| 108 | + soc { |
| 109 | + #address-cells = <2>; |
| 110 | + #size-cells = <2>; |
| 111 | +
|
| 112 | + pcie@1c00000 { |
| 113 | + compatible = "qcom,pcie-sm8350"; |
| 114 | + reg = <0 0x01c00000 0 0x3000>, |
| 115 | + <0 0x60000000 0 0xf1d>, |
| 116 | + <0 0x60000f20 0 0xa8>, |
| 117 | + <0 0x60001000 0 0x1000>, |
| 118 | + <0 0x60100000 0 0x100000>; |
| 119 | + reg-names = "parf", "dbi", "elbi", "atu", "config"; |
| 120 | + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, |
| 121 | + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; |
| 122 | +
|
| 123 | + bus-range = <0x00 0xff>; |
| 124 | + device_type = "pci"; |
| 125 | + linux,pci-domain = <0>; |
| 126 | + num-lanes = <1>; |
| 127 | +
|
| 128 | + #address-cells = <3>; |
| 129 | + #size-cells = <2>; |
| 130 | +
|
| 131 | + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, |
| 132 | + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, |
| 133 | + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, |
| 134 | + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, |
| 135 | + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, |
| 136 | + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, |
| 137 | + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, |
| 138 | + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, |
| 139 | + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; |
| 140 | + clock-names = "aux", |
| 141 | + "cfg", |
| 142 | + "bus_master", |
| 143 | + "bus_slave", |
| 144 | + "slave_q2a", |
| 145 | + "tbu", |
| 146 | + "ddrss_sf_tbu", |
| 147 | + "aggre1", |
| 148 | + "aggre0"; |
| 149 | +
|
| 150 | + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, |
| 151 | + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 152 | + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, |
| 153 | + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, |
| 154 | + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, |
| 155 | + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, |
| 156 | + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, |
| 157 | + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; |
| 158 | + interrupt-names = "msi0", "msi1", "msi2", "msi3", |
| 159 | + "msi4", "msi5", "msi6", "msi7"; |
| 160 | + #interrupt-cells = <1>; |
| 161 | + interrupt-map-mask = <0 0 0 0x7>; |
| 162 | + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ |
| 163 | + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ |
| 164 | + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ |
| 165 | + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ |
| 166 | +
|
| 167 | + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, |
| 168 | + <0x100 &apps_smmu 0x1c01 0x1>; |
| 169 | +
|
| 170 | + phys = <&pcie0_phy>; |
| 171 | + phy-names = "pciephy"; |
| 172 | +
|
| 173 | + pinctrl-0 = <&pcie0_default_state>; |
| 174 | + pinctrl-names = "default"; |
| 175 | +
|
| 176 | + power-domains = <&gcc PCIE_0_GDSC>; |
| 177 | +
|
| 178 | + resets = <&gcc GCC_PCIE_0_BCR>; |
| 179 | + reset-names = "pci"; |
| 180 | +
|
| 181 | + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; |
| 182 | + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; |
| 183 | + }; |
| 184 | + }; |
0 commit comments