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Marek Vasutrobherring
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dt-bindings: imx6q-pcie: Handle various clock configurations
The i.MX SoCs have various clock configurations routed into the PCIe IP, the list of clock is below. Document all those configurations in the DT binding document. All SoCs: pcie, pcie_bus 6QDL, 7D: + pcie_phy 6SX: + pcie_phy pcie_inbound_axi 8MQ: + pcie_phy pcie_aux 8MM, 8MP: + pcie_aux Reviewed-by: Rob Herring <[email protected]> Acked-by: Alexander Stein <[email protected]> Signed-off-by: Marek Vasut <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]>
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Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml

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@@ -57,7 +57,7 @@ properties:
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items:
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- const: pcie
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- const: pcie_bus
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- const: pcie_phy
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- enum: [ pcie_phy, pcie_aux ]
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- enum: [ pcie_inbound_axi, pcie_aux ]
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num-lanes:
@@ -185,7 +185,7 @@ allOf:
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items:
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- {}
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- {}
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- {}
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- const: pcie_phy
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- const: pcie_inbound_axi
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- if:
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properties:
@@ -198,7 +198,7 @@ allOf:
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items:
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- {}
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- {}
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- {}
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- const: pcie_phy
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- const: pcie_aux
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- if:
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properties:
@@ -208,10 +208,41 @@ allOf:
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enum:
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- fsl,imx6sx-pcie
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- fsl,imx8mq-pcie
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then:
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properties:
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clocks:
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maxItems: 3
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clock-names:
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maxItems: 3
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx6q-pcie
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- fsl,imx6qp-pcie
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- fsl,imx7d-pcie
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then:
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properties:
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clock-names:
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maxItems: 3
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contains:
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const: pcie_phy
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8mm-pcie
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- fsl,imx8mp-pcie
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then:
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properties:
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clock-names:
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maxItems: 3
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contains:
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const: pcie_aux
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unevaluatedProperties: false
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