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1 | 1 | // SPDX-License-Identifier: GPL-2.0
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| 2 | +#include <dt-bindings/clock/mediatek,mtmips-sysc.h> |
2 | 3 |
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3 | 4 | / {
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4 | 5 | #address-cells = <1>;
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16 | 17 | };
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17 | 18 | };
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18 | 19 |
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19 |
| - resetc: reset-controller { |
20 |
| - compatible = "ralink,rt2880-reset"; |
21 |
| - #reset-cells = <1>; |
22 |
| - }; |
23 |
| - |
24 | 20 | cpuintc: interrupt-controller {
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25 | 21 | #address-cells = <0>;
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26 | 22 | #interrupt-cells = <1>;
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36 | 32 | #address-cells = <1>;
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37 | 33 | #size-cells = <1>;
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38 | 34 |
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39 |
| - sysc: system-controller@0 { |
40 |
| - compatible = "ralink,mt7620a-sysc", "syscon"; |
| 35 | + sysc: syscon@0 { |
| 36 | + compatible = "ralink,mt7628-sysc", "syscon"; |
41 | 37 | reg = <0x0 0x60>;
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| 38 | + #clock-cells = <1>; |
| 39 | + #reset-cells = <1>; |
42 | 40 | };
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43 | 41 |
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44 | 42 | pinmux: pinmux@60 {
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138 | 136 | compatible = "mediatek,mt7621-wdt";
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139 | 137 | reg = <0x100 0x30>;
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140 | 138 |
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141 |
| - resets = <&resetc 8>; |
| 139 | + resets = <&sysc 8>; |
142 | 140 | reset-names = "wdt";
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143 | 141 |
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144 | 142 | interrupt-parent = <&intc>;
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154 | 152 | interrupt-controller;
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155 | 153 | #interrupt-cells = <1>;
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156 | 154 |
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157 |
| - resets = <&resetc 9>; |
| 155 | + resets = <&sysc 9>; |
158 | 156 | reset-names = "intc";
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159 | 157 |
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160 | 158 | interrupt-parent = <&cpuintc>;
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190 | 188 | pinctrl-names = "default";
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191 | 189 | pinctrl-0 = <&pinmux_spi_spi>;
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192 | 190 |
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193 |
| - resets = <&resetc 18>; |
| 191 | + clocks = <&sysc MT76X8_CLK_SPI1>; |
| 192 | + |
| 193 | + resets = <&sysc 18>; |
194 | 194 | reset-names = "spi";
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195 | 195 |
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196 | 196 | #address-cells = <1>;
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206 | 206 | pinctrl-names = "default";
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207 | 207 | pinctrl-0 = <&pinmux_i2c_i2c>;
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208 | 208 |
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209 |
| - resets = <&resetc 16>; |
| 209 | + clocks = <&sysc MT76X8_CLK_I2C>; |
| 210 | + |
| 211 | + resets = <&sysc 16>; |
210 | 212 | reset-names = "i2c";
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211 | 213 |
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212 | 214 | #address-cells = <1>;
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222 | 224 | pinctrl-names = "default";
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223 | 225 | pinctrl-0 = <&pinmux_uart0_uart>;
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224 | 226 |
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225 |
| - resets = <&resetc 12>; |
| 227 | + clocks = <&sysc MT76X8_CLK_UART0>; |
| 228 | + |
| 229 | + resets = <&sysc 12>; |
226 | 230 | reset-names = "uart0";
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227 | 231 |
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228 | 232 | interrupt-parent = <&intc>;
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238 | 242 | pinctrl-names = "default";
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239 | 243 | pinctrl-0 = <&pinmux_uart1_uart>;
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240 | 244 |
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241 |
| - resets = <&resetc 19>; |
| 245 | + clocks = <&sysc MT76X8_CLK_UART1>; |
| 246 | + |
| 247 | + resets = <&sysc 19>; |
242 | 248 | reset-names = "uart1";
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243 | 249 |
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244 | 250 | interrupt-parent = <&intc>;
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254 | 260 | pinctrl-names = "default";
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255 | 261 | pinctrl-0 = <&pinmux_uart2_uart>;
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256 | 262 |
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257 |
| - resets = <&resetc 20>; |
| 263 | + clocks = <&sysc MT76X8_CLK_UART2>; |
| 264 | + |
| 265 | + resets = <&sysc 20>; |
258 | 266 | reset-names = "uart2";
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259 | 267 |
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260 | 268 | interrupt-parent = <&intc>;
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271 | 279 | #phy-cells = <0>;
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272 | 280 |
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273 | 281 | ralink,sysctl = <&sysc>;
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274 |
| - resets = <&resetc 22 &resetc 25>; |
| 282 | + resets = <&sysc 22 &sysc 25>; |
275 | 283 | reset-names = "host", "device";
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276 | 284 | };
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277 | 285 |
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290 | 298 | compatible = "mediatek,mt7628-wmac";
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291 | 299 | reg = <0x10300000 0x100000>;
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292 | 300 |
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| 301 | + clocks = <&sysc MT76X8_CLK_WMAC>; |
| 302 | + |
293 | 303 | interrupt-parent = <&cpuintc>;
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294 | 304 | interrupts = <6>;
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295 | 305 |
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