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98 | 98 | #define RCAR_IRQ_STOP (MST)
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99 | 99 |
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100 | 100 | #define ID_LAST_MSG (1 << 0)
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101 |
| -#define ID_FIRST_MSG (1 << 1) |
102 | 101 | #define ID_DONE (1 << 2)
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103 | 102 | #define ID_ARBLOST (1 << 3)
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104 | 103 | #define ID_NACK (1 << 4)
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@@ -333,41 +332,47 @@ static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv)
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333 | 332 | return 0;
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334 | 333 | }
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335 | 334 |
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| 335 | +/* |
| 336 | + * We don't have a test case but the HW engineers say that the write order of |
| 337 | + * ICMSR and ICMCR depends on whether we issue START or REP_START. So, ICMSR |
| 338 | + * handling is outside of this function. First messages clear ICMSR before this |
| 339 | + * function, interrupt handlers clear the relevant bits after this function. |
| 340 | + */ |
336 | 341 | static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
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337 | 342 | {
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338 | 343 | int read = !!rcar_i2c_is_recv(priv);
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339 | 344 |
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340 | 345 | priv->pos = 0;
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| 346 | + priv->flags &= ID_P_MASK; |
| 347 | + |
341 | 348 | if (priv->msgs_left == 1)
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342 | 349 | priv->flags |= ID_LAST_MSG;
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343 | 350 |
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344 | 351 | rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg));
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345 | 352 | if (!priv->atomic_xfer)
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346 | 353 | rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
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347 | 354 |
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348 |
| - /* |
349 |
| - * We don't have a test case but the HW engineers say that the write order |
350 |
| - * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since |
351 |
| - * it didn't cause a drawback for me, let's rather be safe than sorry. |
352 |
| - */ |
353 |
| - if (priv->flags & ID_FIRST_MSG) { |
354 |
| - rcar_i2c_write(priv, ICMSR, 0); |
| 355 | + if (priv->flags & ID_P_REP_AFTER_RD) |
| 356 | + priv->flags &= ~ID_P_REP_AFTER_RD; |
| 357 | + else |
355 | 358 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
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356 |
| - } else { |
357 |
| - if (priv->flags & ID_P_REP_AFTER_RD) |
358 |
| - priv->flags &= ~ID_P_REP_AFTER_RD; |
359 |
| - else |
360 |
| - rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); |
361 |
| - /* ICMSR is cleared in interrupt handlers */ |
362 |
| - } |
| 359 | +} |
| 360 | + |
| 361 | +static void rcar_i2c_first_msg(struct rcar_i2c_priv *priv, |
| 362 | + struct i2c_msg *msgs, int num) |
| 363 | +{ |
| 364 | + priv->msg = msgs; |
| 365 | + priv->msgs_left = num; |
| 366 | + rcar_i2c_write(priv, ICMSR, 0); /* must be before preparing msg */ |
| 367 | + rcar_i2c_prepare_msg(priv); |
363 | 368 | }
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364 | 369 |
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365 | 370 | static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
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366 | 371 | {
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367 | 372 | priv->msg++;
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368 | 373 | priv->msgs_left--;
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369 |
| - priv->flags &= ID_P_MASK; |
370 | 374 | rcar_i2c_prepare_msg(priv);
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| 375 | + /* ICMSR handling must come afterwards in the irq handler */ |
371 | 376 | }
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372 | 377 |
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373 | 378 | static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv, bool terminate)
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@@ -852,11 +857,7 @@ static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
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852 | 857 | for (i = 0; i < num; i++)
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853 | 858 | rcar_i2c_request_dma(priv, msgs + i);
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854 | 859 |
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855 |
| - /* init first message */ |
856 |
| - priv->msg = msgs; |
857 |
| - priv->msgs_left = num; |
858 |
| - priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG; |
859 |
| - rcar_i2c_prepare_msg(priv); |
| 860 | + rcar_i2c_first_msg(priv, msgs, num); |
860 | 861 |
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861 | 862 | time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE,
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862 | 863 | num * adap->timeout);
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@@ -906,12 +907,7 @@ static int rcar_i2c_master_xfer_atomic(struct i2c_adapter *adap,
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906 | 907 | goto out;
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907 | 908 |
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908 | 909 | rcar_i2c_init(priv);
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909 |
| - |
910 |
| - /* init first message */ |
911 |
| - priv->msg = msgs; |
912 |
| - priv->msgs_left = num; |
913 |
| - priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG; |
914 |
| - rcar_i2c_prepare_msg(priv); |
| 910 | + rcar_i2c_first_msg(priv, msgs, num); |
915 | 911 |
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916 | 912 | j = jiffies + num * adap->timeout;
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917 | 913 | do {
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