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bebarinobebarino
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Merge tag 'clk-renesas-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven: - Add Crypto clocks on R-Car M3-W/W+, M3-N, E3, and D3 - Add RPC (QSPI/HyperFLASH) clocks on R-Car H3, M3-W/W+, and M3-N * tag 'clk-renesas-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: Remove use of ARCH_R8A7795 clk: renesas: r8a77965: Add RPC clocks clk: renesas: r8a7796: Add RPC clocks clk: renesas: r8a7795: Add RPC clocks clk: renesas: rcar-gen3: Add CCREE clocks
2 parents bb6d3fb + 068e7f8 commit 23b6bc7

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6 files changed

+34
-2
lines changed

6 files changed

+34
-2
lines changed

‎drivers/clk/renesas/Kconfig

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ config CLK_RENESAS
2020
select CLK_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
2121
select CLK_R8A7792 if ARCH_R8A7792
2222
select CLK_R8A7794 if ARCH_R8A7794
23-
select CLK_R8A7795 if ARCH_R8A77950 || ARCH_R8A77951 || ARCH_R8A7795
23+
select CLK_R8A7795 if ARCH_R8A77950 || ARCH_R8A77951
2424
select CLK_R8A77960 if ARCH_R8A77960
2525
select CLK_R8A77961 if ARCH_R8A77961
2626
select CLK_R8A77965 if ARCH_R8A77965

‎drivers/clk/renesas/r8a7795-cpg-mssr.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,7 @@ enum clk_ids {
4444
CLK_S3,
4545
CLK_SDSRC,
4646
CLK_SSPSRC,
47+
CLK_RPCSRC,
4748
CLK_RINT,
4849

4950
/* Module Clocks */
@@ -70,6 +71,12 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
7071
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
7172
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
7273
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
74+
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
75+
76+
DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC,
77+
CLK_RPCSRC),
78+
DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
79+
R8A7795_CLK_RPC),
7380

7481
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
7582

@@ -242,6 +249,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
242249
DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
243250
DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
244251
DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
252+
DEF_MOD("rpc-if", 917, R8A7795_CLK_RPCD2),
245253
DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6),
246254
DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6),
247255
DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),

‎drivers/clk/renesas/r8a7796-cpg-mssr.c

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,7 @@ enum clk_ids {
4646
CLK_S3,
4747
CLK_SDSRC,
4848
CLK_SSPSRC,
49+
CLK_RPCSRC,
4950
CLK_RINT,
5051

5152
/* Module Clocks */
@@ -72,6 +73,12 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
7273
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
7374
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
7475
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
76+
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
77+
78+
DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC,
79+
CLK_RPCSRC),
80+
DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
81+
R8A7796_CLK_RPC),
7582

7683
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
7784

@@ -105,6 +112,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
105112
DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
106113

107114
DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
115+
DEF_FIXED("cr", R8A7796_CLK_CR, CLK_PLL1_DIV4, 2, 1),
108116
DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
109117
DEF_FIXED("cpex", R8A7796_CLK_CPEX, CLK_EXTAL, 2, 1),
110118

@@ -132,6 +140,7 @@ static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
132140
DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S3D1),
133141
DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S3D1),
134142
DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3),
143+
DEF_MOD("sceg-pub", 229, R8A7796_CLK_CR),
135144
DEF_MOD("cmt3", 300, R8A7796_CLK_R),
136145
DEF_MOD("cmt2", 301, R8A7796_CLK_R),
137146
DEF_MOD("cmt1", 302, R8A7796_CLK_R),
@@ -215,6 +224,7 @@ static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
215224
DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2),
216225
DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4),
217226
DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4),
227+
DEF_MOD("rpc-if", 917, R8A7796_CLK_RPCD2),
218228
DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6),
219229
DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6),
220230
DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP),

‎drivers/clk/renesas/r8a77965-cpg-mssr.c

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,7 @@ enum clk_ids {
4343
CLK_S3,
4444
CLK_SDSRC,
4545
CLK_SSPSRC,
46+
CLK_RPCSRC,
4647
CLK_RINT,
4748

4849
/* Module Clocks */
@@ -68,6 +69,12 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
6869
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
6970
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
7071
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
72+
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
73+
74+
DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC,
75+
CLK_RPCSRC),
76+
DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
77+
R8A77965_CLK_RPC),
7178

7279
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
7380

@@ -99,7 +106,8 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
99106
DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268),
100107
DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c),
101108

102-
DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1),
109+
DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1),
110+
DEF_FIXED("cr", R8A77965_CLK_CR, CLK_PLL1_DIV4, 2, 1),
103111
DEF_FIXED("cp", R8A77965_CLK_CP, CLK_EXTAL, 2, 1),
104112
DEF_FIXED("cpex", R8A77965_CLK_CPEX, CLK_EXTAL, 2, 1),
105113

@@ -127,6 +135,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
127135
DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S3D1),
128136
DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S3D1),
129137
DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),
138+
DEF_MOD("sceg-pub", 229, R8A77965_CLK_CR),
130139

131140
DEF_MOD("cmt3", 300, R8A77965_CLK_R),
132141
DEF_MOD("cmt2", 301, R8A77965_CLK_R),
@@ -215,6 +224,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
215224
DEF_MOD("can-fd", 914, R8A77965_CLK_S3D2),
216225
DEF_MOD("can-if1", 915, R8A77965_CLK_S3D4),
217226
DEF_MOD("can-if0", 916, R8A77965_CLK_S3D4),
227+
DEF_MOD("rpc-if", 917, R8A77965_CLK_RPCD2),
218228
DEF_MOD("i2c6", 918, R8A77965_CLK_S0D6),
219229
DEF_MOD("i2c5", 919, R8A77965_CLK_S0D6),
220230
DEF_MOD("i2c-dvfs", 926, R8A77965_CLK_CP),

‎drivers/clk/renesas/r8a77990-cpg-mssr.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -105,6 +105,7 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
105105
DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, CLK_SDSRC, 0x026c),
106106

107107
DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1),
108+
DEF_FIXED("cr", R8A77990_CLK_CR, CLK_PLL1D2, 2, 1),
108109
DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1),
109110
DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1),
110111

@@ -135,6 +136,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
135136
DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1),
136137
DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1),
137138
DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1),
139+
DEF_MOD("sceg-pub", 229, R8A77990_CLK_CR),
138140

139141
DEF_MOD("cmt3", 300, R8A77990_CLK_R),
140142
DEF_MOD("cmt2", 301, R8A77990_CLK_R),

‎drivers/clk/renesas/r8a77995-cpg-mssr.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -91,6 +91,7 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
9191
DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1),
9292

9393
DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
94+
DEF_FIXED("cr", R8A77995_CLK_CR, CLK_PLL1D2, 2, 1),
9495
DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
9596
DEF_FIXED("cpex", R8A77995_CLK_CPEX, CLK_EXTAL, 4, 1),
9697

@@ -122,6 +123,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
122123
DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
123124
DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
124125
DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
126+
DEF_MOD("sceg-pub", 229, R8A77995_CLK_CR),
125127
DEF_MOD("cmt3", 300, R8A77995_CLK_R),
126128
DEF_MOD("cmt2", 301, R8A77995_CLK_R),
127129
DEF_MOD("cmt1", 302, R8A77995_CLK_R),

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