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bebarinobebarino
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Merge branches 'clk-mediatek', 'clk-imx', 'clk-amlogic' and 'clk-at91' into clk-next
* clk-mediatek: clk: mediatek: mux: Update parent at enable time clk: mediatek: mux: Drop unused clock ops clk: mediatek: Select all the MT8183 clocks by default * clk-imx: dt-bindings: clock: imx: Switch to my personal address MAINTAINERS: Add section for NXP i.MX clock drivers clk: imx: Move 'imx6sl_set_wait_clk()'s prototype out to accessible header clk: imx8mn: add clkout1/2 support clk: imx8mm: add clkout1/2 support clk: imx8mq: add PLL monitor output clk: imx: clk-imx31: Remove unused static const table 'uart_clks' clk: imx6q: demote warning about pre-boot ldb_di_clk reparenting clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystems clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2() clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks * clk-amlogic: clk: meson: axg: Remove MIPI enable clock gate clk: meson-axg: remove CLKID_MIPI_ENABLE dt-bindings: clock: meson8b: remove non-existing clock macros clk: meson: meson8b: remove compatibility code for old .dtbs clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate() clk: meson: clk-pll: make "ret" a signed integer clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLL * clk-at91: clk: at91: Fix the declaration of the clocks
5 parents ee6b84a + 31a42c2 + fb7acfe + e3272b0 + 428d97e commit 242d8cf

37 files changed

+217
-172
lines changed

‎Documentation/devicetree/bindings/clock/imx27-clock.yaml

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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Clock bindings for Freescale i.MX27
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maintainers:
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- Fabio Estevam <fabio.estevam@nxp.com>
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- Fabio Estevam <festevam@gmail.com>
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description: |
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The clock consumer should specify the desired clock by having the clock

‎Documentation/devicetree/bindings/clock/imx31-clock.yaml

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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Clock bindings for Freescale i.MX31
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maintainers:
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- Fabio Estevam <fabio.estevam@nxp.com>
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- Fabio Estevam <festevam@gmail.com>
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description: |
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The clock consumer should specify the desired clock by having the clock

‎Documentation/devicetree/bindings/clock/imx5-clock.yaml

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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Clock bindings for Freescale i.MX5
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maintainers:
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- Fabio Estevam <fabio.estevam@nxp.com>
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- Fabio Estevam <festevam@gmail.com>
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description: |
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The clock consumer should specify the desired clock by having the clock

‎MAINTAINERS

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@@ -12751,6 +12751,13 @@ F: drivers/iio/gyro/fxas21002c_core.c
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F: drivers/iio/gyro/fxas21002c_i2c.c
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F: drivers/iio/gyro/fxas21002c_spi.c
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NXP i.MX CLOCK DRIVERS
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M: Abel Vesa <[email protected]>
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L: [email protected]
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L: [email protected]
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S: Maintained
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F: drivers/clk/imx/
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NXP i.MX 8MQ DCSS DRIVER
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M: Laurentiu Palcu <[email protected]>
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R: Lucas Stach <[email protected]>

‎arch/arm/mach-imx/common.h

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@@ -85,7 +85,6 @@ void imx_anatop_pre_suspend(void);
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void imx_anatop_post_resume(void);
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int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);
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void imx6_set_int_mem_clk_lpm(bool enable);
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void imx6sl_set_wait_clk(bool enter);
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int imx_mmdc_get_ddr_type(void);
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int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode);
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‎arch/arm/mach-imx/cpuidle-imx6sl.c

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@@ -3,6 +3,7 @@
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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*/
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#include <linux/clk/imx.h>
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#include <linux/cpuidle.h>
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#include <linux/module.h>
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#include <asm/cpuidle.h>

‎arch/arm/mach-imx/pm-imx6.c

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@@ -4,6 +4,7 @@
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* Copyright 2011 Linaro Ltd.
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*/
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#include <linux/clk/imx.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>

‎drivers/clk/at91/at91rm9200.c

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@@ -215,5 +215,4 @@ static void __init at91rm9200_pmc_setup(struct device_node *np)
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* deferring properly. Once this is fixed, this can be switched to a platform
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* driver.
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*/
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CLK_OF_DECLARE_DRIVER(at91rm9200_pmc, "atmel,at91rm9200-pmc",
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at91rm9200_pmc_setup);
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CLK_OF_DECLARE(at91rm9200_pmc, "atmel,at91rm9200-pmc", at91rm9200_pmc_setup);

‎drivers/clk/at91/at91sam9260.c

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Original file line numberDiff line numberDiff line change
@@ -491,26 +491,26 @@ static void __init at91sam9260_pmc_setup(struct device_node *np)
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{
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at91sam926x_pmc_setup(np, &at91sam9260_data);
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}
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CLK_OF_DECLARE_DRIVER(at91sam9260_pmc, "atmel,at91sam9260-pmc",
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at91sam9260_pmc_setup);
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CLK_OF_DECLARE(at91sam9260_pmc, "atmel,at91sam9260-pmc", at91sam9260_pmc_setup);
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static void __init at91sam9261_pmc_setup(struct device_node *np)
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{
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at91sam926x_pmc_setup(np, &at91sam9261_data);
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}
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CLK_OF_DECLARE_DRIVER(at91sam9261_pmc, "atmel,at91sam9261-pmc",
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at91sam9261_pmc_setup);
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CLK_OF_DECLARE(at91sam9261_pmc, "atmel,at91sam9261-pmc", at91sam9261_pmc_setup);
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static void __init at91sam9263_pmc_setup(struct device_node *np)
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{
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at91sam926x_pmc_setup(np, &at91sam9263_data);
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}
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CLK_OF_DECLARE_DRIVER(at91sam9263_pmc, "atmel,at91sam9263-pmc",
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at91sam9263_pmc_setup);
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CLK_OF_DECLARE(at91sam9263_pmc, "atmel,at91sam9263-pmc", at91sam9263_pmc_setup);
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static void __init at91sam9g20_pmc_setup(struct device_node *np)
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{
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at91sam926x_pmc_setup(np, &at91sam9g20_data);
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}
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CLK_OF_DECLARE_DRIVER(at91sam9g20_pmc, "atmel,at91sam9g20-pmc",
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at91sam9g20_pmc_setup);
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CLK_OF_DECLARE(at91sam9g20_pmc, "atmel,at91sam9g20-pmc", at91sam9g20_pmc_setup);

‎drivers/clk/at91/at91sam9g45.c

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@@ -228,5 +228,4 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np)
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* The TCB is used as the clocksource so its clock is needed early. This means
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* this can't be a platform driver.
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*/
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CLK_OF_DECLARE_DRIVER(at91sam9g45_pmc, "atmel,at91sam9g45-pmc",
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at91sam9g45_pmc_setup);
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CLK_OF_DECLARE(at91sam9g45_pmc, "atmel,at91sam9g45-pmc", at91sam9g45_pmc_setup);

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