Skip to content

Commit 24816cc

Browse files
Jon Pan-Dohbjorn-helgaas
authored andcommitted
PCI/AER: Add ratelimits to PCI AER Documentation
Add ratelimits section for rationale and defaults. [bhelgaas: note fatal errors are not ratelimited] Signed-off-by: Karolina Stolarek <[email protected]> Signed-off-by: Jon Pan-Doh <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Tested-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Kuppuswamy Sathyanarayanan <[email protected]> Acked-by: Paul E. McKenney <[email protected]> Link: https://patch.msgid.link/[email protected]
1 parent a57f2bf commit 24816cc

File tree

1 file changed

+12
-0
lines changed

1 file changed

+12
-0
lines changed

Documentation/PCI/pcieaer-howto.rst

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -85,6 +85,18 @@ In the example, 'Requester ID' means the ID of the device that sent
8585
the error message to the Root Port. Please refer to PCIe specs for other
8686
fields.
8787

88+
AER Ratelimits
89+
--------------
90+
91+
Since error messages can be generated for each transaction, we may see
92+
large volumes of errors reported. To prevent spammy devices from flooding
93+
the console/stalling execution, messages are throttled by device and error
94+
type (correctable vs. non-fatal uncorrectable). Fatal errors, including
95+
DPC errors, are not ratelimited.
96+
97+
AER uses the default ratelimit of DEFAULT_RATELIMIT_BURST (10 events) over
98+
DEFAULT_RATELIMIT_INTERVAL (5 seconds).
99+
88100
AER Statistics / Counters
89101
-------------------------
90102

0 commit comments

Comments
 (0)