66#include <linux/etherdevice.h>
77#include <linux/init.h>
88#include <linux/interrupt.h>
9- #include <linux/irq.h>
109#include <linux/kernel.h>
1110#include <linux/module.h>
1211#include <linux/netdevice.h>
@@ -3585,17 +3584,6 @@ static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf,
35853584 return ret ;
35863585}
35873586
3588- static void hclge_set_reset_pending (struct hclge_dev * hdev ,
3589- enum hnae3_reset_type reset_type )
3590- {
3591- /* When an incorrect reset type is executed, the get_reset_level
3592- * function generates the HNAE3_NONE_RESET flag. As a result, this
3593- * type do not need to pending.
3594- */
3595- if (reset_type != HNAE3_NONE_RESET )
3596- set_bit (reset_type , & hdev -> reset_pending );
3597- }
3598-
35993587static u32 hclge_check_event_cause (struct hclge_dev * hdev , u32 * clearval )
36003588{
36013589 u32 cmdq_src_reg , msix_src_reg , hw_err_src_reg ;
@@ -3616,7 +3604,7 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
36163604 */
36173605 if (BIT (HCLGE_VECTOR0_IMPRESET_INT_B ) & msix_src_reg ) {
36183606 dev_info (& hdev -> pdev -> dev , "IMP reset interrupt\n" );
3619- hclge_set_reset_pending ( hdev , HNAE3_IMP_RESET );
3607+ set_bit ( HNAE3_IMP_RESET , & hdev -> reset_pending );
36203608 set_bit (HCLGE_COMM_STATE_CMD_DISABLE , & hdev -> hw .hw .comm_state );
36213609 * clearval = BIT (HCLGE_VECTOR0_IMPRESET_INT_B );
36223610 hdev -> rst_stats .imp_rst_cnt ++ ;
@@ -3626,7 +3614,7 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
36263614 if (BIT (HCLGE_VECTOR0_GLOBALRESET_INT_B ) & msix_src_reg ) {
36273615 dev_info (& hdev -> pdev -> dev , "global reset interrupt\n" );
36283616 set_bit (HCLGE_COMM_STATE_CMD_DISABLE , & hdev -> hw .hw .comm_state );
3629- hclge_set_reset_pending ( hdev , HNAE3_GLOBAL_RESET );
3617+ set_bit ( HNAE3_GLOBAL_RESET , & hdev -> reset_pending );
36303618 * clearval = BIT (HCLGE_VECTOR0_GLOBALRESET_INT_B );
36313619 hdev -> rst_stats .global_rst_cnt ++ ;
36323620 return HCLGE_VECTOR0_EVENT_RST ;
@@ -3781,7 +3769,7 @@ static int hclge_misc_irq_init(struct hclge_dev *hdev)
37813769 snprintf (hdev -> misc_vector .name , HNAE3_INT_NAME_LEN , "%s-misc-%s" ,
37823770 HCLGE_NAME , pci_name (hdev -> pdev ));
37833771 ret = request_irq (hdev -> misc_vector .vector_irq , hclge_misc_irq_handle ,
3784- IRQ_NOAUTOEN , hdev -> misc_vector .name , hdev );
3772+ 0 , hdev -> misc_vector .name , hdev );
37853773 if (ret ) {
37863774 hclge_free_vector (hdev , 0 );
37873775 dev_err (& hdev -> pdev -> dev , "request misc irq(%d) fail\n" ,
@@ -4074,7 +4062,7 @@ static void hclge_do_reset(struct hclge_dev *hdev)
40744062 case HNAE3_FUNC_RESET :
40754063 dev_info (& pdev -> dev , "PF reset requested\n" );
40764064 /* schedule again to check later */
4077- hclge_set_reset_pending ( hdev , HNAE3_FUNC_RESET );
4065+ set_bit ( HNAE3_FUNC_RESET , & hdev -> reset_pending );
40784066 hclge_reset_task_schedule (hdev );
40794067 break ;
40804068 default :
@@ -4108,8 +4096,6 @@ static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev,
41084096 clear_bit (HNAE3_FLR_RESET , addr );
41094097 }
41104098
4111- clear_bit (HNAE3_NONE_RESET , addr );
4112-
41134099 if (hdev -> reset_type != HNAE3_NONE_RESET &&
41144100 rst_level < hdev -> reset_type )
41154101 return HNAE3_NONE_RESET ;
@@ -4251,7 +4237,7 @@ static bool hclge_reset_err_handle(struct hclge_dev *hdev)
42514237 return false;
42524238 } else if (hdev -> rst_stats .reset_fail_cnt < MAX_RESET_FAIL_CNT ) {
42534239 hdev -> rst_stats .reset_fail_cnt ++ ;
4254- hclge_set_reset_pending (hdev , hdev -> reset_type );
4240+ set_bit (hdev -> reset_type , & hdev -> reset_pending );
42554241 dev_info (& hdev -> pdev -> dev ,
42564242 "re-schedule reset task(%u)\n" ,
42574243 hdev -> rst_stats .reset_fail_cnt );
@@ -4494,20 +4480,8 @@ static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
44944480static void hclge_set_def_reset_request (struct hnae3_ae_dev * ae_dev ,
44954481 enum hnae3_reset_type rst_type )
44964482{
4497- #define HCLGE_SUPPORT_RESET_TYPE \
4498- (BIT(HNAE3_FLR_RESET) | BIT(HNAE3_FUNC_RESET) | \
4499- BIT(HNAE3_GLOBAL_RESET) | BIT(HNAE3_IMP_RESET))
4500-
45014483 struct hclge_dev * hdev = ae_dev -> priv ;
45024484
4503- if (!(BIT (rst_type ) & HCLGE_SUPPORT_RESET_TYPE )) {
4504- /* To prevent reset triggered by hclge_reset_event */
4505- set_bit (HNAE3_NONE_RESET , & hdev -> default_reset_request );
4506- dev_warn (& hdev -> pdev -> dev , "unsupported reset type %d\n" ,
4507- rst_type );
4508- return ;
4509- }
4510-
45114485 set_bit (rst_type , & hdev -> default_reset_request );
45124486}
45134487
@@ -11917,6 +11891,9 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
1191711891
1191811892 hclge_init_rxd_adv_layout (hdev );
1191911893
11894+ /* Enable MISC vector(vector0) */
11895+ hclge_enable_vector (& hdev -> misc_vector , true);
11896+
1192011897 ret = hclge_init_wol (hdev );
1192111898 if (ret )
1192211899 dev_warn (& pdev -> dev ,
@@ -11929,10 +11906,6 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
1192911906 hclge_state_init (hdev );
1193011907 hdev -> last_reset_time = jiffies ;
1193111908
11932- /* Enable MISC vector(vector0) */
11933- enable_irq (hdev -> misc_vector .vector_irq );
11934- hclge_enable_vector (& hdev -> misc_vector , true);
11935-
1193611909 dev_info (& hdev -> pdev -> dev , "%s driver initialization finished.\n" ,
1193711910 HCLGE_DRIVER_NAME );
1193811911
@@ -12338,7 +12311,7 @@ static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
1233812311
1233912312 /* Disable MISC vector(vector0) */
1234012313 hclge_enable_vector (& hdev -> misc_vector , false);
12341- disable_irq (hdev -> misc_vector .vector_irq );
12314+ synchronize_irq (hdev -> misc_vector .vector_irq );
1234212315
1234312316 /* Disable all hw interrupts */
1234412317 hclge_config_mac_tnl_int (hdev , false);
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