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irqchip: Add T-HEAD C900 ACLINT SSWI driver
Add a driver for the T-HEAD C900 ACLINT SSWI device. This device allows the system with T-HEAD cpus to send ipi via fast device interface. Signed-off-by: Inochi Amaoto <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/all/[email protected]
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‎drivers/irqchip/Kconfig

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@@ -619,6 +619,18 @@ config STARFIVE_JH8100_INTC
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If you don't know what to do here, say Y.
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config THEAD_C900_ACLINT_SSWI
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bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller"
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depends on RISCV
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depends on SMP
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select IRQ_DOMAIN_HIERARCHY
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select GENERIC_IRQ_IPI_MUX
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help
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This enables support for T-HEAD specific ACLINT SSWI device
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support.
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If you don't know what to do here, say Y.
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config EXYNOS_IRQ_COMBINER
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bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
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depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST

‎drivers/irqchip/Makefile

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@@ -103,6 +103,7 @@ obj-$(CONFIG_RISCV_APLIC_MSI) += irq-riscv-aplic-msi.o
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obj-$(CONFIG_RISCV_IMSIC) += irq-riscv-imsic-state.o irq-riscv-imsic-early.o irq-riscv-imsic-platform.o
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obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o
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obj-$(CONFIG_STARFIVE_JH8100_INTC) += irq-starfive-jh8100-intc.o
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obj-$(CONFIG_THEAD_C900_ACLINT_SSWI) += irq-thead-c900-aclint-sswi.o
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obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o
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obj-$(CONFIG_IMX_INTMUX) += irq-imx-intmux.o
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obj-$(CONFIG_IMX_MU_MSI) += irq-imx-mu-msi.o

‎drivers/irqchip/irq-thead-c900-aclint-sswi.c

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2024 Inochi Amaoto <[email protected]>
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*/
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#define pr_fmt(fmt) "thead-c900-aclint-sswi: " fmt
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#include <linux/cpu.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#include <linux/smp.h>
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#include <linux/string_choices.h>
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#include <asm/sbi.h>
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#include <asm/vendorid_list.h>
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#define THEAD_ACLINT_xSWI_REGISTER_SIZE 4
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#define THEAD_C9XX_CSR_SXSTATUS 0x5c0
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#define THEAD_C9XX_SXSTATUS_CLINTEE BIT(17)
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static int sswi_ipi_virq __ro_after_init;
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static DEFINE_PER_CPU(void __iomem *, sswi_cpu_regs);
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static void thead_aclint_sswi_ipi_send(unsigned int cpu)
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{
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writel_relaxed(0x1, per_cpu(sswi_cpu_regs, cpu));
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}
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static void thead_aclint_sswi_ipi_clear(void)
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{
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writel_relaxed(0x0, this_cpu_read(sswi_cpu_regs));
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}
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static void thead_aclint_sswi_ipi_handle(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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chained_irq_enter(chip, desc);
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csr_clear(CSR_IP, IE_SIE);
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thead_aclint_sswi_ipi_clear();
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ipi_mux_process();
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chained_irq_exit(chip, desc);
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}
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static int thead_aclint_sswi_starting_cpu(unsigned int cpu)
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{
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enable_percpu_irq(sswi_ipi_virq, irq_get_trigger_type(sswi_ipi_virq));
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return 0;
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}
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static int thead_aclint_sswi_dying_cpu(unsigned int cpu)
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{
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thead_aclint_sswi_ipi_clear();
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disable_percpu_irq(sswi_ipi_virq);
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return 0;
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}
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static int __init thead_aclint_sswi_parse_irq(struct fwnode_handle *fwnode,
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void __iomem *reg)
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{
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struct of_phandle_args parent;
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unsigned long hartid;
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u32 contexts, i;
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int rc, cpu;
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contexts = of_irq_count(to_of_node(fwnode));
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if (!(contexts)) {
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pr_err("%pfwP: no ACLINT SSWI context available\n", fwnode);
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return -EINVAL;
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}
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for (i = 0; i < contexts; i++) {
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rc = of_irq_parse_one(to_of_node(fwnode), i, &parent);
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if (rc)
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return rc;
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rc = riscv_of_parent_hartid(parent.np, &hartid);
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if (rc)
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return rc;
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if (parent.args[0] != RV_IRQ_SOFT)
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return -ENOTSUPP;
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cpu = riscv_hartid_to_cpuid(hartid);
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per_cpu(sswi_cpu_regs, cpu) = reg + i * THEAD_ACLINT_xSWI_REGISTER_SIZE;
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}
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pr_info("%pfwP: register %u CPU%s\n", fwnode, contexts, str_plural(contexts));
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return 0;
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}
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static int __init thead_aclint_sswi_probe(struct fwnode_handle *fwnode)
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{
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struct irq_domain *domain;
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void __iomem *reg;
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int virq, rc;
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/* If it is T-HEAD CPU, check whether SSWI is enabled */
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if (riscv_cached_mvendorid(0) == THEAD_VENDOR_ID &&
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!(csr_read(THEAD_C9XX_CSR_SXSTATUS) & THEAD_C9XX_SXSTATUS_CLINTEE))
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return -ENOTSUPP;
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if (!is_of_node(fwnode))
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return -EINVAL;
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reg = of_iomap(to_of_node(fwnode), 0);
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if (!reg)
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return -ENOMEM;
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/* Parse SSWI setting */
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rc = thead_aclint_sswi_parse_irq(fwnode, reg);
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if (rc < 0)
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return rc;
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/* If mulitple SSWI devices are present, do not register irq again */
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if (sswi_ipi_virq)
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return 0;
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/* Find riscv intc domain and create IPI irq mapping */
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domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(), DOMAIN_BUS_ANY);
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if (!domain) {
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pr_err("%pfwP: Failed to find INTC domain\n", fwnode);
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return -ENOENT;
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}
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sswi_ipi_virq = irq_create_mapping(domain, RV_IRQ_SOFT);
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if (!sswi_ipi_virq) {
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pr_err("unable to create ACLINT SSWI IRQ mapping\n");
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return -ENOMEM;
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}
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/* Register SSWI irq and handler */
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virq = ipi_mux_create(BITS_PER_BYTE, thead_aclint_sswi_ipi_send);
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if (virq <= 0) {
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pr_err("unable to create muxed IPIs\n");
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irq_dispose_mapping(sswi_ipi_virq);
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return virq < 0 ? virq : -ENOMEM;
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}
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irq_set_chained_handler(sswi_ipi_virq, thead_aclint_sswi_ipi_handle);
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cpuhp_setup_state(CPUHP_AP_IRQ_THEAD_ACLINT_SSWI_STARTING,
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"irqchip/thead-aclint-sswi:starting",
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thead_aclint_sswi_starting_cpu,
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thead_aclint_sswi_dying_cpu);
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riscv_ipi_set_virq_range(virq, BITS_PER_BYTE);
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/* Announce that SSWI is providing IPIs */
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pr_info("providing IPIs using THEAD ACLINT SSWI\n");
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return 0;
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}
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static int __init thead_aclint_sswi_early_probe(struct device_node *node,
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struct device_node *parent)
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{
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return thead_aclint_sswi_probe(&node->fwnode);
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}
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IRQCHIP_DECLARE(thead_aclint_sswi, "thead,c900-aclint-sswi", thead_aclint_sswi_early_probe);

‎include/linux/cpuhotplug.h

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@@ -147,6 +147,7 @@ enum cpuhp_state {
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CPUHP_AP_IRQ_EIOINTC_STARTING,
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CPUHP_AP_IRQ_AVECINTC_STARTING,
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CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
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CPUHP_AP_IRQ_THEAD_ACLINT_SSWI_STARTING,
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CPUHP_AP_IRQ_RISCV_IMSIC_STARTING,
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CPUHP_AP_IRQ_RISCV_SBI_IPI_STARTING,
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CPUHP_AP_ARM_MVEBU_COHERENCY,

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