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drm/i915/dpio: Give VLV DPIO group register a clearer name
Include _GRP in VLV DPIO PHY group access register define names. Makes it more obvious where the accesses will land. Also matches the naming used by BXT already. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
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-62
lines changed

2 files changed

+62
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lines changed

‎drivers/gpu/drm/i915/display/intel_dpio_phy.c

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1071,18 +1071,18 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
10711071

10721072
vlv_dpio_get(dev_priv);
10731073

1074-
vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), 0x00000000);
1075-
vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch), demph_reg_value);
1076-
vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(ch),
1074+
vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), 0x00000000);
1075+
vlv_dpio_write(dev_priv, phy, VLV_TX_DW4_GRP(ch), demph_reg_value);
1076+
vlv_dpio_write(dev_priv, phy, VLV_TX_DW2_GRP(ch),
10771077
uniqtranscale_reg_value);
1078-
vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(ch), 0x0C782040);
1078+
vlv_dpio_write(dev_priv, phy, VLV_TX_DW3_GRP(ch), 0x0C782040);
10791079

10801080
if (tx3_demph)
10811081
vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(ch), tx3_demph);
10821082

1083-
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(ch), 0x00030000);
1084-
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(ch), preemph_reg_value);
1085-
vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), DPIO_TX_OCALINIT_EN);
1083+
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11_GRP(ch), 0x00030000);
1084+
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value);
1085+
vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN);
10861086

10871087
vlv_dpio_put(dev_priv);
10881088
}
@@ -1098,19 +1098,19 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
10981098
/* Program Tx lane resets to default */
10991099
vlv_dpio_get(dev_priv);
11001100

1101-
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch),
1101+
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch),
11021102
DPIO_PCS_TX_LANE2_RESET |
11031103
DPIO_PCS_TX_LANE1_RESET);
1104-
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch),
1104+
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch),
11051105
DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
11061106
DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
11071107
(1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
11081108
DPIO_PCS_CLK_SOFT_RESET);
11091109

11101110
/* Fix up inter-pair skew failure */
1111-
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12(ch), 0x00750f00);
1112-
vlv_dpio_write(dev_priv, phy, VLV_TX_DW11(ch), 0x00001500);
1113-
vlv_dpio_write(dev_priv, phy, VLV_TX_DW14(ch), 0x40400000);
1111+
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12_GRP(ch), 0x00750f00);
1112+
vlv_dpio_write(dev_priv, phy, VLV_TX_DW11_GRP(ch), 0x00001500);
1113+
vlv_dpio_write(dev_priv, phy, VLV_TX_DW14_GRP(ch), 0x40400000);
11141114

11151115
vlv_dpio_put(dev_priv);
11161116
}
@@ -1136,11 +1136,11 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
11361136
else
11371137
val &= ~(1<<21);
11381138
val |= 0x001000c4;
1139-
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(ch), val);
1139+
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8_GRP(ch), val);
11401140

11411141
/* Program lane clock */
1142-
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14(ch), 0x00760018);
1143-
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23(ch), 0x00400888);
1142+
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14_GRP(ch), 0x00760018);
1143+
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23_GRP(ch), 0x00400888);
11441144

11451145
vlv_dpio_put(dev_priv);
11461146
}
@@ -1154,7 +1154,7 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder,
11541154
enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
11551155

11561156
vlv_dpio_get(dev_priv);
1157-
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch), 0x00000000);
1158-
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch), 0x00e00060);
1157+
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch), 0x00000000);
1158+
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060);
11591159
vlv_dpio_put(dev_priv);
11601160
}

‎drivers/gpu/drm/i915/i915_reg.h

Lines changed: 45 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -254,13 +254,13 @@
254254
* Per DDI channel DPIO regs
255255
*/
256256

257-
#define _VLV_PCS_DW0_CH0 0x8200
258-
#define _VLV_PCS_DW0_CH1 0x8400
257+
#define _VLV_PCS_DW0_CH0_GRP 0x8200
258+
#define _VLV_PCS_DW0_CH1_GRP 0x8400
259259
#define DPIO_PCS_TX_LANE2_RESET (1 << 16)
260260
#define DPIO_PCS_TX_LANE1_RESET (1 << 7)
261261
#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4)
262262
#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
263-
#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
263+
#define VLV_PCS_DW0_GRP(ch) _PORT(ch, _VLV_PCS_DW0_CH0_GRP, _VLV_PCS_DW0_CH1_GRP)
264264

265265
#define _VLV_PCS01_DW0_CH0 0x200
266266
#define _VLV_PCS23_DW0_CH0 0x400
@@ -269,14 +269,14 @@
269269
#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
270270
#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
271271

272-
#define _VLV_PCS_DW1_CH0 0x8204
273-
#define _VLV_PCS_DW1_CH1 0x8404
272+
#define _VLV_PCS_DW1_CH0_GRP 0x8204
273+
#define _VLV_PCS_DW1_CH1_GRP 0x8404
274274
#define CHV_PCS_REQ_SOFTRESET_EN (1 << 23)
275275
#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
276276
#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
277277
#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
278278
#define DPIO_PCS_CLK_SOFT_RESET (1 << 5)
279-
#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
279+
#define VLV_PCS_DW1_GRP(ch) _PORT(ch, _VLV_PCS_DW1_CH0_GRP, _VLV_PCS_DW1_CH1_GRP)
280280

281281
#define _VLV_PCS01_DW1_CH0 0x204
282282
#define _VLV_PCS23_DW1_CH0 0x404
@@ -285,11 +285,11 @@
285285
#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
286286
#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
287287

288-
#define _VLV_PCS_DW8_CH0 0x8220
289-
#define _VLV_PCS_DW8_CH1 0x8420
288+
#define _VLV_PCS_DW8_CH0_GRP 0x8220
289+
#define _VLV_PCS_DW8_CH1_GRP 0x8420
290290
#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
291291
#define CHV_PCS_USEDCLKCHANNEL (1 << 21)
292-
#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
292+
#define VLV_PCS_DW8_GRP(ch) _PORT(ch, _VLV_PCS_DW8_CH0_GRP, _VLV_PCS_DW8_CH1_GRP)
293293

294294
#define _VLV_PCS01_DW8_CH0 0x0220
295295
#define _VLV_PCS23_DW8_CH0 0x0420
@@ -298,15 +298,15 @@
298298
#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
299299
#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
300300

301-
#define _VLV_PCS_DW9_CH0 0x8224
302-
#define _VLV_PCS_DW9_CH1 0x8424
301+
#define _VLV_PCS_DW9_CH0_GRP 0x8224
302+
#define _VLV_PCS_DW9_CH1_GRP 0x8424
303303
#define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13)
304304
#define DPIO_PCS_TX2MARGIN_000 (0 << 13)
305305
#define DPIO_PCS_TX2MARGIN_101 (1 << 13)
306306
#define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10)
307307
#define DPIO_PCS_TX1MARGIN_000 (0 << 10)
308308
#define DPIO_PCS_TX1MARGIN_101 (1 << 10)
309-
#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
309+
#define VLV_PCS_DW9_GRP(ch) _PORT(ch, _VLV_PCS_DW9_CH0_GRP, _VLV_PCS_DW9_CH1_GRP)
310310

311311
#define _VLV_PCS01_DW9_CH0 0x224
312312
#define _VLV_PCS23_DW9_CH0 0x424
@@ -315,8 +315,8 @@
315315
#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
316316
#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
317317

318-
#define _CHV_PCS_DW10_CH0 0x8228
319-
#define _CHV_PCS_DW10_CH1 0x8428
318+
#define _CHV_PCS_DW10_CH0_GRP 0x8228
319+
#define _CHV_PCS_DW10_CH1_GRP 0x8428
320320
#define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30)
321321
#define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31)
322322
#define DPIO_PCS_TX2DEEMP_MASK (0xf << 24)
@@ -325,7 +325,7 @@
325325
#define DPIO_PCS_TX1DEEMP_MASK (0xf << 16)
326326
#define DPIO_PCS_TX1DEEMP_9P5 (0 << 16)
327327
#define DPIO_PCS_TX1DEEMP_6P0 (2 << 16)
328-
#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
328+
#define CHV_PCS_DW10_GRP(ch) _PORT(ch, _CHV_PCS_DW10_CH0_GRP, _CHV_PCS_DW10_CH1_GRP)
329329

330330
#define _VLV_PCS01_DW10_CH0 0x0228
331331
#define _VLV_PCS23_DW10_CH0 0x0428
@@ -334,13 +334,13 @@
334334
#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
335335
#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
336336

337-
#define _VLV_PCS_DW11_CH0 0x822c
338-
#define _VLV_PCS_DW11_CH1 0x842c
337+
#define _VLV_PCS_DW11_CH0_GRP 0x822c
338+
#define _VLV_PCS_DW11_CH1_GRP 0x842c
339339
#define DPIO_TX2_STAGGER_MASK(x) ((x) << 24)
340340
#define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3)
341341
#define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1)
342342
#define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0)
343-
#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
343+
#define VLV_PCS_DW11_GRP(ch) _PORT(ch, _VLV_PCS_DW11_CH0_GRP, _VLV_PCS_DW11_CH1_GRP)
344344

345345
#define _VLV_PCS01_DW11_CH0 0x022c
346346
#define _VLV_PCS23_DW11_CH0 0x042c
@@ -356,64 +356,64 @@
356356
#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
357357
#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
358358

359-
#define _VLV_PCS_DW12_CH0 0x8230
360-
#define _VLV_PCS_DW12_CH1 0x8430
359+
#define _VLV_PCS_DW12_CH0_GRP 0x8230
360+
#define _VLV_PCS_DW12_CH1_GRP 0x8430
361361
#define DPIO_TX2_STAGGER_MULT(x) ((x) << 20)
362362
#define DPIO_TX1_STAGGER_MULT(x) ((x) << 16)
363363
#define DPIO_TX1_STAGGER_MASK(x) ((x) << 8)
364364
#define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6)
365365
#define DPIO_LANESTAGGER_STRAP(x) ((x) << 0)
366-
#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
366+
#define VLV_PCS_DW12_GRP(ch) _PORT(ch, _VLV_PCS_DW12_CH0_GRP, _VLV_PCS_DW12_CH1_GRP)
367367

368-
#define _VLV_PCS_DW14_CH0 0x8238
369-
#define _VLV_PCS_DW14_CH1 0x8438
370-
#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
368+
#define _VLV_PCS_DW14_CH0_GRP 0x8238
369+
#define _VLV_PCS_DW14_CH1_GRP 0x8438
370+
#define VLV_PCS_DW14_GRP(ch) _PORT(ch, _VLV_PCS_DW14_CH0_GRP, _VLV_PCS_DW14_CH1_GRP)
371371

372372
#define VLV_PCS_DW17_BCAST 0xc044
373373

374-
#define _VLV_PCS_DW23_CH0 0x825c
375-
#define _VLV_PCS_DW23_CH1 0x845c
376-
#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
374+
#define _VLV_PCS_DW23_CH0_GRP 0x825c
375+
#define _VLV_PCS_DW23_CH1_GRP 0x845c
376+
#define VLV_PCS_DW23_GRP(ch) _PORT(ch, _VLV_PCS_DW23_CH0_GRP, _VLV_PCS_DW23_CH1_GRP)
377377

378-
#define _VLV_TX_DW2_CH0 0x8288
379-
#define _VLV_TX_DW2_CH1 0x8488
378+
#define _VLV_TX_DW2_CH0_GRP 0x8288
379+
#define _VLV_TX_DW2_CH1_GRP 0x8488
380380
#define DPIO_SWING_MARGIN000_SHIFT 16
381381
#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
382382
#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
383-
#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
383+
#define VLV_TX_DW2_GRP(ch) _PORT(ch, _VLV_TX_DW2_CH0_GRP, _VLV_TX_DW2_CH1_GRP)
384384

385-
#define _VLV_TX_DW3_CH0 0x828c
386-
#define _VLV_TX_DW3_CH1 0x848c
385+
#define _VLV_TX_DW3_CH0_GRP 0x828c
386+
#define _VLV_TX_DW3_CH1_GRP 0x848c
387387
/* The following bit for CHV phy */
388388
#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27)
389389
#define DPIO_SWING_MARGIN101_SHIFT 16
390390
#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
391-
#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
391+
#define VLV_TX_DW3_GRP(ch) _PORT(ch, _VLV_TX_DW3_CH0_GRP, _VLV_TX_DW3_CH1_GRP)
392392

393-
#define _VLV_TX_DW4_CH0 0x8290
394-
#define _VLV_TX_DW4_CH1 0x8490
393+
#define _VLV_TX_DW4_CH0_GRP 0x8290
394+
#define _VLV_TX_DW4_CH1_GRP 0x8490
395395
#define DPIO_SWING_DEEMPH9P5_SHIFT 24
396396
#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
397397
#define DPIO_SWING_DEEMPH6P0_SHIFT 16
398398
#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
399-
#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
399+
#define VLV_TX_DW4_GRP(ch) _PORT(ch, _VLV_TX_DW4_CH0_GRP, _VLV_TX_DW4_CH1_GRP)
400400

401401
#define _VLV_TX3_DW4_CH0 0x690
402402
#define _VLV_TX3_DW4_CH1 0x2a90
403403
#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
404404

405-
#define _VLV_TX_DW5_CH0 0x8294
406-
#define _VLV_TX_DW5_CH1 0x8494
405+
#define _VLV_TX_DW5_CH0_GRP 0x8294
406+
#define _VLV_TX_DW5_CH1_GRP 0x8494
407407
#define DPIO_TX_OCALINIT_EN (1 << 31)
408-
#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
408+
#define VLV_TX_DW5_GRP(ch) _PORT(ch, _VLV_TX_DW5_CH0_GRP, _VLV_TX_DW5_CH1_GRP)
409409

410-
#define _VLV_TX_DW11_CH0 0x82ac
411-
#define _VLV_TX_DW11_CH1 0x84ac
412-
#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
410+
#define _VLV_TX_DW11_CH0_GRP 0x82ac
411+
#define _VLV_TX_DW11_CH1_GRP 0x84ac
412+
#define VLV_TX_DW11_GRP(ch) _PORT(ch, _VLV_TX_DW11_CH0_GRP, _VLV_TX_DW11_CH1_GRP)
413413

414-
#define _VLV_TX_DW14_CH0 0x82b8
415-
#define _VLV_TX_DW14_CH1 0x84b8
416-
#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
414+
#define _VLV_TX_DW14_CH0_GRP 0x82b8
415+
#define _VLV_TX_DW14_CH1_GRP 0x84b8
416+
#define VLV_TX_DW14_GRP(ch) _PORT(ch, _VLV_TX_DW14_CH0_GRP, _VLV_TX_DW14_CH1_GRP)
417417

418418
/* CHV dpPhy registers */
419419
#define _CHV_PLL_DW0_CH0 0x8000

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