drm/amd/display: Fixing DIG FIFO Error

Leo Chen · alexdeucher · commit 269aad0919c7 · 2022-09-13T14:26:59.000-04:00
[Why &amp; How]
DIG_FIFO_READ_START_LEVEL should only be set to default value (7) by software.
Removed all instances of resetting the register to 0

Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Reviewed-by: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Acked-by: Pavle Kotarac &lt;Pavle.Kotarac@amd.com&gt;
Signed-off-by: Leo Chen &lt;sancchen@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c
@@ -67,8 +67,7 @@ static void enc314_disable_fifo(struct stream_encoder *enc)
 {
 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 
-	REG_UPDATE_2(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0,
-		     DIG_FIFO_READ_START_LEVEL, 0);
+	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0);
 }
 
 static void enc314_dp_set_odm_combine(

Original file line number	Diff line number	Diff line change
`@@ -67,8 +67,7 @@ static void enc314_disable_fifo(struct stream_encoder *enc)`
`67`	`67`	`{`
`68`	`68`	`struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);`
`69`	`69`
`70`		`- REG_UPDATE_2(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0,`
`71`		`- DIG_FIFO_READ_START_LEVEL, 0);`
	`70`	`+ REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0);`
`72`	`71`	`}`
`73`	`72`
`74`	`73`	`static void enc314_dp_set_odm_combine(`