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Georgi Djakov
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Merge branch 'icc-sc8280xp-l3' into icc-next
The SC8280XP currently shows depressing results in memory benchmarks. Fix this by introducing support for the platform in the OSM (and EPSS) L3 driver and support for the platform in the bwmon binding. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Georgi Djakov <[email protected]>
2 parents c1c537c + 2d710b0 commit 26e90ec

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‎Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,10 +24,15 @@ properties:
2424
oneOf:
2525
- items:
2626
- enum:
27-
- qcom,sc7280-bwmon
27+
- qcom,sc7280-cpu-bwmon
28+
- qcom,sc8280xp-cpu-bwmon
2829
- qcom,sdm845-bwmon
2930
- const: qcom,msm8998-bwmon
3031
- const: qcom,msm8998-bwmon # BWMON v4
32+
- items:
33+
- enum:
34+
- qcom,sc8280xp-llcc-bwmon
35+
- const: qcom,sc7280-llcc-bwmon
3136
- const: qcom,sc7280-llcc-bwmon # BWMON v5
3237
- const: qcom,sdm845-llcc-bwmon # BWMON v5
3338

‎Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml

Lines changed: 16 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -16,13 +16,21 @@ description:
1616

1717
properties:
1818
compatible:
19-
enum:
20-
- qcom,sc7180-osm-l3
21-
- qcom,sc7280-epss-l3
22-
- qcom,sc8180x-osm-l3
23-
- qcom,sdm845-osm-l3
24-
- qcom,sm8150-osm-l3
25-
- qcom,sm8250-epss-l3
19+
oneOf:
20+
- items:
21+
- enum:
22+
- qcom,sc7180-osm-l3
23+
- qcom,sc8180x-osm-l3
24+
- qcom,sdm845-osm-l3
25+
- qcom,sm8150-osm-l3
26+
- const: qcom,osm-l3
27+
- items:
28+
- enum:
29+
- qcom,sc7280-epss-l3
30+
- qcom,sc8280xp-epss-l3
31+
- qcom,sm8250-epss-l3
32+
- qcom,sm8350-epss-l3
33+
- const: qcom,epss-l3
2634

2735
reg:
2836
maxItems: 1
@@ -56,7 +64,7 @@ examples:
5664
#define RPMH_CXO_CLK 0
5765
5866
osm_l3: interconnect@17d41000 {
59-
compatible = "qcom,sdm845-osm-l3";
67+
compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
6068
reg = <0x17d41000 0x1400>;
6169
6270
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;

‎drivers/interconnect/qcom/osm-l3.c

Lines changed: 35 additions & 91 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@
3434

3535
/* EPSS Register offsets */
3636
#define EPSS_LUT_ROW_SIZE 4
37+
#define EPSS_REG_L3_VOTE 0x90
3738
#define EPSS_REG_FREQ_LUT 0x100
3839
#define EPSS_REG_PERF_STATE 0x320
3940

@@ -74,6 +75,11 @@ struct qcom_osm_l3_desc {
7475
unsigned int reg_perf_state;
7576
};
7677

78+
enum {
79+
OSM_L3_MASTER_NODE = 10000,
80+
OSM_L3_SLAVE_NODE,
81+
};
82+
7783
#define DEFINE_QNODE(_name, _id, _buswidth, ...) \
7884
static const struct qcom_osm_l3_node _name = { \
7985
.name = #_name, \
@@ -83,123 +89,59 @@ struct qcom_osm_l3_desc {
8389
.links = { __VA_ARGS__ }, \
8490
}
8591

86-
DEFINE_QNODE(sdm845_osm_apps_l3, SDM845_MASTER_OSM_L3_APPS, 16, SDM845_SLAVE_OSM_L3);
87-
DEFINE_QNODE(sdm845_osm_l3, SDM845_SLAVE_OSM_L3, 16);
88-
89-
static const struct qcom_osm_l3_node * const sdm845_osm_l3_nodes[] = {
90-
[MASTER_OSM_L3_APPS] = &sdm845_osm_apps_l3,
91-
[SLAVE_OSM_L3] = &sdm845_osm_l3,
92-
};
92+
DEFINE_QNODE(osm_l3_master, OSM_L3_MASTER_NODE, 16, OSM_L3_SLAVE_NODE);
93+
DEFINE_QNODE(osm_l3_slave, OSM_L3_SLAVE_NODE, 16);
9394

94-
static const struct qcom_osm_l3_desc sdm845_icc_osm_l3 = {
95-
.nodes = sdm845_osm_l3_nodes,
96-
.num_nodes = ARRAY_SIZE(sdm845_osm_l3_nodes),
97-
.lut_row_size = OSM_LUT_ROW_SIZE,
98-
.reg_freq_lut = OSM_REG_FREQ_LUT,
99-
.reg_perf_state = OSM_REG_PERF_STATE,
95+
static const struct qcom_osm_l3_node * const osm_l3_nodes[] = {
96+
[MASTER_OSM_L3_APPS] = &osm_l3_master,
97+
[SLAVE_OSM_L3] = &osm_l3_slave,
10098
};
10199

102-
DEFINE_QNODE(sc7180_osm_apps_l3, SC7180_MASTER_OSM_L3_APPS, 16, SC7180_SLAVE_OSM_L3);
103-
DEFINE_QNODE(sc7180_osm_l3, SC7180_SLAVE_OSM_L3, 16);
100+
DEFINE_QNODE(epss_l3_master, OSM_L3_MASTER_NODE, 32, OSM_L3_SLAVE_NODE);
101+
DEFINE_QNODE(epss_l3_slave, OSM_L3_SLAVE_NODE, 32);
104102

105-
static const struct qcom_osm_l3_node * const sc7180_osm_l3_nodes[] = {
106-
[MASTER_OSM_L3_APPS] = &sc7180_osm_apps_l3,
107-
[SLAVE_OSM_L3] = &sc7180_osm_l3,
103+
static const struct qcom_osm_l3_node * const epss_l3_nodes[] = {
104+
[MASTER_EPSS_L3_APPS] = &epss_l3_master,
105+
[SLAVE_EPSS_L3_SHARED] = &epss_l3_slave,
108106
};
109107

110-
static const struct qcom_osm_l3_desc sc7180_icc_osm_l3 = {
111-
.nodes = sc7180_osm_l3_nodes,
112-
.num_nodes = ARRAY_SIZE(sc7180_osm_l3_nodes),
108+
static const struct qcom_osm_l3_desc osm_l3 = {
109+
.nodes = osm_l3_nodes,
110+
.num_nodes = ARRAY_SIZE(osm_l3_nodes),
113111
.lut_row_size = OSM_LUT_ROW_SIZE,
114112
.reg_freq_lut = OSM_REG_FREQ_LUT,
115113
.reg_perf_state = OSM_REG_PERF_STATE,
116114
};
117115

118-
DEFINE_QNODE(sc7280_epss_apps_l3, SC7280_MASTER_EPSS_L3_APPS, 32, SC7280_SLAVE_EPSS_L3);
119-
DEFINE_QNODE(sc7280_epss_l3, SC7280_SLAVE_EPSS_L3, 32);
120-
121-
static const struct qcom_osm_l3_node * const sc7280_epss_l3_nodes[] = {
122-
[MASTER_EPSS_L3_APPS] = &sc7280_epss_apps_l3,
123-
[SLAVE_EPSS_L3_SHARED] = &sc7280_epss_l3,
124-
};
125-
126-
static const struct qcom_osm_l3_desc sc7280_icc_epss_l3 = {
127-
.nodes = sc7280_epss_l3_nodes,
128-
.num_nodes = ARRAY_SIZE(sc7280_epss_l3_nodes),
116+
static const struct qcom_osm_l3_desc epss_l3_perf_state = {
117+
.nodes = epss_l3_nodes,
118+
.num_nodes = ARRAY_SIZE(epss_l3_nodes),
129119
.lut_row_size = EPSS_LUT_ROW_SIZE,
130120
.reg_freq_lut = EPSS_REG_FREQ_LUT,
131121
.reg_perf_state = EPSS_REG_PERF_STATE,
132122
};
133123

134-
DEFINE_QNODE(sc8180x_osm_apps_l3, SC8180X_MASTER_OSM_L3_APPS, 32, SC8180X_SLAVE_OSM_L3);
135-
DEFINE_QNODE(sc8180x_osm_l3, SC8180X_SLAVE_OSM_L3, 32);
136-
137-
static const struct qcom_osm_l3_node * const sc8180x_osm_l3_nodes[] = {
138-
[MASTER_OSM_L3_APPS] = &sc8180x_osm_apps_l3,
139-
[SLAVE_OSM_L3] = &sc8180x_osm_l3,
140-
};
141-
142-
static const struct qcom_osm_l3_desc sc8180x_icc_osm_l3 = {
143-
.nodes = sc8180x_osm_l3_nodes,
144-
.num_nodes = ARRAY_SIZE(sc8180x_osm_l3_nodes),
145-
.lut_row_size = OSM_LUT_ROW_SIZE,
146-
.reg_freq_lut = OSM_REG_FREQ_LUT,
147-
.reg_perf_state = OSM_REG_PERF_STATE,
148-
};
149-
150-
DEFINE_QNODE(sm8150_osm_apps_l3, SM8150_MASTER_OSM_L3_APPS, 32, SM8150_SLAVE_OSM_L3);
151-
DEFINE_QNODE(sm8150_osm_l3, SM8150_SLAVE_OSM_L3, 32);
152-
153-
static const struct qcom_osm_l3_node * const sm8150_osm_l3_nodes[] = {
154-
[MASTER_OSM_L3_APPS] = &sm8150_osm_apps_l3,
155-
[SLAVE_OSM_L3] = &sm8150_osm_l3,
156-
};
157-
158-
static const struct qcom_osm_l3_desc sm8150_icc_osm_l3 = {
159-
.nodes = sm8150_osm_l3_nodes,
160-
.num_nodes = ARRAY_SIZE(sm8150_osm_l3_nodes),
161-
.lut_row_size = OSM_LUT_ROW_SIZE,
162-
.reg_freq_lut = OSM_REG_FREQ_LUT,
163-
.reg_perf_state = OSM_REG_PERF_STATE,
164-
};
165-
166-
DEFINE_QNODE(sm8250_epss_apps_l3, SM8250_MASTER_EPSS_L3_APPS, 32, SM8250_SLAVE_EPSS_L3);
167-
DEFINE_QNODE(sm8250_epss_l3, SM8250_SLAVE_EPSS_L3, 32);
168-
169-
static const struct qcom_osm_l3_node * const sm8250_epss_l3_nodes[] = {
170-
[MASTER_EPSS_L3_APPS] = &sm8250_epss_apps_l3,
171-
[SLAVE_EPSS_L3_SHARED] = &sm8250_epss_l3,
172-
};
173-
174-
static const struct qcom_osm_l3_desc sm8250_icc_epss_l3 = {
175-
.nodes = sm8250_epss_l3_nodes,
176-
.num_nodes = ARRAY_SIZE(sm8250_epss_l3_nodes),
124+
static const struct qcom_osm_l3_desc epss_l3_l3_vote = {
125+
.nodes = epss_l3_nodes,
126+
.num_nodes = ARRAY_SIZE(epss_l3_nodes),
177127
.lut_row_size = EPSS_LUT_ROW_SIZE,
178128
.reg_freq_lut = EPSS_REG_FREQ_LUT,
179-
.reg_perf_state = EPSS_REG_PERF_STATE,
129+
.reg_perf_state = EPSS_REG_L3_VOTE,
180130
};
181131

182132
static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst)
183133
{
184134
struct qcom_osm_l3_icc_provider *qp;
185135
struct icc_provider *provider;
186136
const struct qcom_osm_l3_node *qn;
187-
struct icc_node *n;
188137
unsigned int index;
189-
u32 agg_peak = 0;
190-
u32 agg_avg = 0;
191138
u64 rate;
192139

193140
qn = src->data;
194141
provider = src->provider;
195142
qp = to_osm_l3_provider(provider);
196143

197-
list_for_each_entry(n, &provider->nodes, node_list)
198-
provider->aggregate(n, 0, n->avg_bw, n->peak_bw,
199-
&agg_avg, &agg_peak);
200-
201-
rate = max(agg_avg, agg_peak);
202-
rate = icc_units_to_bps(rate);
144+
rate = icc_units_to_bps(dst->peak_bw);
203145
do_div(rate, qn->buswidth);
204146

205147
for (index = 0; index < qp->max_state - 1; index++) {
@@ -344,12 +286,14 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
344286
}
345287

346288
static const struct of_device_id osm_l3_of_match[] = {
347-
{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
348-
{ .compatible = "qcom,sc7280-epss-l3", .data = &sc7280_icc_epss_l3 },
349-
{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
350-
{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
351-
{ .compatible = "qcom,sc8180x-osm-l3", .data = &sc8180x_icc_osm_l3 },
352-
{ .compatible = "qcom,sm8250-epss-l3", .data = &sm8250_icc_epss_l3 },
289+
{ .compatible = "qcom,epss-l3", .data = &epss_l3_l3_vote },
290+
{ .compatible = "qcom,osm-l3", .data = &osm_l3 },
291+
{ .compatible = "qcom,sc7180-osm-l3", .data = &osm_l3 },
292+
{ .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3_perf_state },
293+
{ .compatible = "qcom,sdm845-osm-l3", .data = &osm_l3 },
294+
{ .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 },
295+
{ .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 },
296+
{ .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3_perf_state },
353297
{ }
354298
};
355299
MODULE_DEVICE_TABLE(of, osm_l3_of_match);

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