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Merge tag 'edac_for_5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp
Pull EDAC updates from Borislav Petkov: - amd64_edac: Family 0x17, models 0x30-.. enablement (Yazen Ghannam) - skx_*: Librarize it so that it can be shared between drivers (Qiuxu Zhuo) - altera: Stratix10 improvements (Thor Thayer) - The usual round of fixes, fixlets and cleanups * tag 'edac_for_5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: Revert "EDAC/amd64: Support more than two controllers for chip select handling" arm64: dts: stratix10: Use new Stratix10 EDAC bindings Documentation: dt: edac: Add Stratix10 Peripheral bindings Documentation: dt: edac: Fix Stratix10 IRQ bindings EDAC/altera, firmware/intel: Add Stratix10 ECC DBE SMC call EDAC/altera: Initialize peripheral FIFOs in probe() EDAC/altera: Do less intrusive error injection EDAC/amd64: Adjust printed chip select sizes when interleaved EDAC/amd64: Support more than two controllers for chip select handling EDAC/amd64: Recognize x16 symbol size EDAC/amd64: Set maximum channel layer size depending on family EDAC/amd64: Support more than two Unified Memory Controllers EDAC/amd64: Use a macro for iterating over Unified Memory Controllers EDAC/amd64: Add Family 17h Model 30h PCI IDs MAINTAINERS: Add entry for EDAC-I10NM MAINTAINERS: Update entry for EDAC-SKYLAKE EDAC, altera: Fix S10 Double Bit Error Notification EDAC, skx, i10nm: Make skx_common.c a pure library
2 parents 4dd2ab9 + 8de9930 commit 275b103

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‎Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt

Lines changed: 125 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -232,37 +232,152 @@ Example:
232232
};
233233
};
234234

235-
Stratix10 SoCFPGA ECC Manager
235+
Stratix10 SoCFPGA ECC Manager (ARM64)
236236
The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
237-
in a shared register similar to the Arria10. However, ECC requires
238-
access to registers that can only be read from Secure Monitor with
239-
SMC calls. Therefore the device tree is slightly different.
237+
in a shared register similar to the Arria10. However, Stratix10 ECC
238+
requires access to registers that can only be read from Secure Monitor
239+
with SMC calls. Therefore the device tree is slightly different. Note
240+
that only 1 interrupt is sent in Stratix10 because the double bit errors
241+
are treated as SErrors in ARM64 instead of IRQs in ARM32.
240242

241243
Required Properties:
242244
- compatible : Should be "altr,socfpga-s10-ecc-manager"
243-
- interrupts : Should be single bit error interrupt, then double bit error
244-
interrupt.
245+
- altr,sysgr-syscon : phandle to Stratix10 System Manager Block
246+
containing the ECC manager registers.
247+
- interrupts : Should be single bit error interrupt.
245248
- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
246249
- #interrupt-cells : must be set to 2.
250+
- #address-cells: must be 1
251+
- #size-cells: must be 1
252+
- ranges : standard definition, should translate from local addresses
247253

248254
Subcomponents:
249255

250256
SDRAM ECC
251257
Required Properties:
252258
- compatible : Should be "altr,sdram-edac-s10"
253-
- interrupts : Should be single bit error interrupt, then double bit error
254-
interrupt, in this order.
259+
- interrupts : Should be single bit error interrupt.
260+
261+
On-Chip RAM ECC
262+
Required Properties:
263+
- compatible : Should be "altr,socfpga-s10-ocram-ecc"
264+
- reg : Address and size for ECC block registers.
265+
- altr,ecc-parent : phandle to parent OCRAM node.
266+
- interrupts : Should be single bit error interrupt.
267+
268+
Ethernet FIFO ECC
269+
Required Properties:
270+
- compatible : Should be "altr,socfpga-s10-eth-mac-ecc"
271+
- reg : Address and size for ECC block registers.
272+
- altr,ecc-parent : phandle to parent Ethernet node.
273+
- interrupts : Should be single bit error interrupt.
274+
275+
NAND FIFO ECC
276+
Required Properties:
277+
- compatible : Should be "altr,socfpga-s10-nand-ecc"
278+
- reg : Address and size for ECC block registers.
279+
- altr,ecc-parent : phandle to parent NAND node.
280+
- interrupts : Should be single bit error interrupt.
281+
282+
DMA FIFO ECC
283+
Required Properties:
284+
- compatible : Should be "altr,socfpga-s10-dma-ecc"
285+
- reg : Address and size for ECC block registers.
286+
- altr,ecc-parent : phandle to parent DMA node.
287+
- interrupts : Should be single bit error interrupt.
288+
289+
USB FIFO ECC
290+
Required Properties:
291+
- compatible : Should be "altr,socfpga-s10-usb-ecc"
292+
- reg : Address and size for ECC block registers.
293+
- altr,ecc-parent : phandle to parent USB node.
294+
- interrupts : Should be single bit error interrupt.
295+
296+
SDMMC FIFO ECC
297+
Required Properties:
298+
- compatible : Should be "altr,socfpga-s10-sdmmc-ecc"
299+
- reg : Address and size for ECC block registers.
300+
- altr,ecc-parent : phandle to parent SD/MMC node.
301+
- interrupts : Should be single bit error interrupt for port A
302+
and then single bit error interrupt for port B.
255303

256304
Example:
257305

258306
eccmgr {
259307
compatible = "altr,socfpga-s10-ecc-manager";
260-
interrupts = <0 15 4>, <0 95 4>;
308+
altr,sysmgr-syscon = <&sysmgr>;
309+
#address-cells = <1>;
310+
#size-cells = <1>;
311+
interrupts = <0 15 4>;
261312
interrupt-controller;
262313
#interrupt-cells = <2>;
314+
ranges;
263315

264316
sdramedac {
265317
compatible = "altr,sdram-edac-s10";
266-
interrupts = <16 4>, <48 4>;
318+
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
319+
};
320+
321+
ocram-ecc@ff8cc000 {
322+
compatible = "altr,socfpga-s10-ocram-ecc";
323+
reg = <ff8cc000 0x100>;
324+
altr,ecc-parent = <&ocram>;
325+
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
326+
};
327+
328+
emac0-rx-ecc@ff8c0000 {
329+
compatible = "altr,socfpga-s10-eth-mac-ecc";
330+
reg = <0xff8c0000 0x100>;
331+
altr,ecc-parent = <&gmac0>;
332+
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
333+
};
334+
335+
emac0-tx-ecc@ff8c0400 {
336+
compatible = "altr,socfpga-s10-eth-mac-ecc";
337+
reg = <0xff8c0400 0x100>;
338+
altr,ecc-parent = <&gmac0>;
339+
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>'
340+
};
341+
342+
nand-buf-ecc@ff8c8000 {
343+
compatible = "altr,socfpga-s10-nand-ecc";
344+
reg = <0xff8c8000 0x100>;
345+
altr,ecc-parent = <&nand>;
346+
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
347+
};
348+
349+
nand-rd-ecc@ff8c8400 {
350+
compatible = "altr,socfpga-s10-nand-ecc";
351+
reg = <0xff8c8400 0x100>;
352+
altr,ecc-parent = <&nand>;
353+
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
354+
};
355+
356+
nand-wr-ecc@ff8c8800 {
357+
compatible = "altr,socfpga-s10-nand-ecc";
358+
reg = <0xff8c8800 0x100>;
359+
altr,ecc-parent = <&nand>;
360+
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
361+
};
362+
363+
dma-ecc@ff8c9000 {
364+
compatible = "altr,socfpga-s10-dma-ecc";
365+
reg = <0xff8c9000 0x100>;
366+
altr,ecc-parent = <&pdma>;
367+
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
368+
369+
usb0-ecc@ff8c4000 {
370+
compatible = "altr,socfpga-s10-usb-ecc";
371+
reg = <0xff8c4000 0x100>;
372+
altr,ecc-parent = <&usb0>;
373+
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
374+
};
375+
376+
sdmmc-ecc@ff8c8c00 {
377+
compatible = "altr,socfpga-s10-sdmmc-ecc";
378+
reg = <0xff8c8c00 0x100>;
379+
altr,ecc-parent = <&mmc>;
380+
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
381+
<15 IRQ_TYPE_LEVEL_HIGH>;
267382
};
268383
};

‎MAINTAINERS

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5599,6 +5599,12 @@ L: [email protected]
55995599
S: Maintained
56005600
F: drivers/edac/ghes_edac.c
56015601

5602+
EDAC-I10NM
5603+
M: Tony Luck <[email protected]>
5604+
L: [email protected]
5605+
S: Maintained
5606+
F: drivers/edac/i10nm_base.c
5607+
56025608
EDAC-I3000
56035609
L: [email protected]
56045610
S: Orphan
@@ -5680,7 +5686,7 @@ EDAC-SKYLAKE
56805686
M: Tony Luck <[email protected]>
56815687
L: [email protected]
56825688
S: Maintained
5683-
F: drivers/edac/skx_edac.c
5689+
F: drivers/edac/skx_*.c
56845690

56855691
EDAC-TI
56865692
M: Tero Kristo <[email protected]>

‎arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi

Lines changed: 13 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -534,43 +534,44 @@
534534
};
535535

536536
eccmgr {
537-
compatible = "altr,socfpga-a10-ecc-manager";
537+
compatible = "altr,socfpga-s10-ecc-manager",
538+
"altr,socfpga-a10-ecc-manager";
538539
altr,sysmgr-syscon = <&sysmgr>;
539540
#address-cells = <1>;
540541
#size-cells = <1>;
541-
interrupts = <0 15 4>, <0 95 4>;
542+
interrupts = <0 15 4>;
542543
interrupt-controller;
543544
#interrupt-cells = <2>;
544545
ranges;
545546

546547
sdramedac {
547548
compatible = "altr,sdram-edac-s10";
548549
altr,sdr-syscon = <&sdr>;
549-
interrupts = <16 4>, <48 4>;
550+
interrupts = <16 4>;
550551
};
551552

552553
usb0-ecc@ff8c4000 {
553-
compatible = "altr,socfpga-usb-ecc";
554+
compatible = "altr,socfpga-s10-usb-ecc",
555+
"altr,socfpga-usb-ecc";
554556
reg = <0xff8c4000 0x100>;
555557
altr,ecc-parent = <&usb0>;
556-
interrupts = <2 4>,
557-
<34 4>;
558+
interrupts = <2 4>;
558559
};
559560

560561
emac0-rx-ecc@ff8c0000 {
561-
compatible = "altr,socfpga-eth-mac-ecc";
562+
compatible = "altr,socfpga-s10-eth-mac-ecc",
563+
"altr,socfpga-eth-mac-ecc";
562564
reg = <0xff8c0000 0x100>;
563565
altr,ecc-parent = <&gmac0>;
564-
interrupts = <4 4>,
565-
<36 4>;
566+
interrupts = <4 4>;
566567
};
567568

568569
emac0-tx-ecc@ff8c0400 {
569-
compatible = "altr,socfpga-eth-mac-ecc";
570+
compatible = "altr,socfpga-s10-eth-mac-ecc",
571+
"altr,socfpga-eth-mac-ecc";
570572
reg = <0xff8c0400 0x100>;
571573
altr,ecc-parent = <&gmac0>;
572-
interrupts = <5 4>,
573-
<37 4>;
574+
interrupts = <5 4>;
574575
};
575576

576577
};

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