Skip to content

Commit 27beb3c

Browse files
torvaldstorvalds
committed
Merge tag 'pci-v6.7-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
Pull pci updates from Bjorn Helgaas: "Enumeration: - Use acpi_evaluate_dsm_typed() instead of open-coding _DSM evaluation to learn device characteristics (Andy Shevchenko) - Tidy multi-function header checks using new PCI_HEADER_TYPE_MASK definition (Ilpo Järvinen) - Simplify config access error checking in various drivers (Ilpo Järvinen) - Use pcie_capability_clear_word() (not pcie_capability_clear_and_set_word()) when only clearing (Ilpo Järvinen) - Add pci_get_base_class() to simplify finding devices using base class only (ignoring subclass and programming interface) (Sui Jingfeng) - Add pci_is_vga(), which includes ancient PCI_CLASS_NOT_DEFINED_VGA devices from before the Class Code was added to PCI (Sui Jingfeng) - Use pci_is_vga() for vgaarb, sysfs "boot_vga", virtio, qxl to include ancient VGA devices (Sui Jingfeng) Resource management: - Make pci_assign_unassigned_resources() non-init because sparc uses it after init (Randy Dunlap) Driver binding: - Retain .remove() and .probe() callbacks (previously __init) because sysfs may cause them to be called later (Uwe Kleine-König) - Prevent xHCI driver from claiming AMD VanGogh USB3 DRD device, so it can be claimed by dwc3 instead (Vicki Pfau) PCI device hotplug: - Add Ampere Altra Attention Indicator extension driver for acpiphp (D Scott Phillips) Power management: - Quirk VideoPropulsion Torrent QN16e with longer delay after reset (Lukas Wunner) - Prevent users from overriding drivers that say we shouldn't use D3cold (Lukas Wunner) - Avoid PME from D3hot/D3cold for AMD Rembrandt and Phoenix USB4 because wakeup interrupts from those states don't work if amd-pmc has put the platform in a hardware sleep state (Mario Limonciello) IOMMU: - Disable ATS for Intel IPU E2000 devices with invalidation message endianness erratum (Bartosz Pawlowski) Error handling: - Factor out interrupt enable/disable into helpers (Kai-Heng Feng) Peer-to-peer DMA: - Fix flexible-array usage in struct pci_p2pdma_pagemap in case we ever use pagemaps with multiple entries (Gustavo A. R. Silva) ASPM: - Revert a change that broke when drivers disabled L1 and users later enabled an L1.x substate via sysfs, and fix a similar issue when users disabled L1 via sysfs (Heiner Kallweit) Endpoint framework: - Fix double free in __pci_epc_create() (Dan Carpenter) - Use IS_ERR_OR_NULL() to simplify endpoint core (Ruan Jinjie) Cadence PCIe controller driver: - Drop unused "is_rc" member (Li Chen) Freescale Layerscape PCIe controller driver: - Enable 64-bit addressing in endpoint mode (Guanhua Gao) Intel VMD host bridge driver: - Fix multi-function header check (Ilpo Järvinen) Microsoft Hyper-V host bridge driver: - Annotate struct hv_dr_state with __counted_by (Kees Cook) NVIDIA Tegra194 PCIe controller driver: - Drop setting of LNKCAP_MLW (max link width) since dw_pcie_setup() already does this via dw_pcie_link_set_max_link_width() (Yoshihiro Shimoda) Qualcomm PCIe controller driver: - Use PCIE_SPEED2MBS_ENC() to simplify encoding of link speed (Manivannan Sadhasivam) - Add a .write_dbi2() callback so DBI2 register writes, e.g., for setting the BAR size, work correctly (Manivannan Sadhasivam) - Enable ASPM for platforms that use 1.9.0 ops, because the PCI core doesn't enable ASPM states that haven't been enabled by the firmware (Manivannan Sadhasivam) Renesas R-Car Gen4 PCIe controller driver: - Add DesignWare core support (set max link width, EDMA_UNROLL flag, .pre_init(), .deinit(), etc) for use by R-Car Gen4 driver (Yoshihiro Shimoda) - Add driver and DT schema for DesignWare-based Renesas R-Car Gen4 controller in both host and endpoint mode (Yoshihiro Shimoda) Xilinx NWL PCIe controller driver: - Update ECAM size to support 256 buses (Thippeswamy Havalige) - Stop setting bridge primary/secondary/subordinate bus numbers, since PCI core does this (Thippeswamy Havalige) Xilinx XDMA controller driver: - Add driver and DT schema for Zynq UltraScale+ MPSoCs devices with Xilinx XDMA Soft IP (Thippeswamy Havalige) Miscellaneous: - Use FIELD_GET()/FIELD_PREP() to simplify and reduce use of _SHIFT macros (Ilpo Järvinen, Bjorn Helgaas) - Remove logic_outb(), _outw(), outl() duplicate declarations (John Sanpe) - Replace unnecessary UTF-8 in Kconfig help text because menuconfig doesn't render it correctly (Liu Song)" * tag 'pci-v6.7-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (102 commits) PCI: qcom-ep: Add dedicated callback for writing to DBI2 registers PCI: Simplify pcie_capability_clear_and_set_word() to ..._clear_word() PCI: endpoint: Fix double free in __pci_epc_create() PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx XDMA PCIe Root Port Bridge PCI: xilinx-cpm: Move IRQ definitions to a common header PCI: xilinx-nwl: Modify ECAM size to enable support for 256 buses PCI: xilinx-nwl: Rename the NWL_ECAM_VALUE_DEFAULT macro dt-bindings: PCI: xilinx-nwl: Modify ECAM size in the DT example PCI: xilinx-nwl: Remove redundant code that sets Type 1 header fields PCI: hotplug: Add Ampere Altra Attention Indicator extension driver PCI/AER: Factor out interrupt toggling into helpers PCI: acpiphp: Allow built-in drivers for Attention Indicators PCI/portdrv: Use FIELD_GET() PCI/VC: Use FIELD_GET() PCI/PTM: Use FIELD_GET() PCI/PME: Use FIELD_GET() PCI/ATS: Use FIELD_GET() PCI/ATS: Show PASID Capability register width in bitmasks PCI/ASPM: Fix L1 substate handling in aspm_attr_store_common() ...
2 parents 4652b8e + 50b3ef1 commit 27beb3c

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

88 files changed

+2613
-511
lines changed

‎Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml

Lines changed: 115 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,115 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
# Copyright (C) 2022-2023 Renesas Electronics Corp.
3+
%YAML 1.2
4+
---
5+
$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-ep.yaml#
6+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7+
8+
title: Renesas R-Car Gen4 PCIe Endpoint
9+
10+
maintainers:
11+
- Yoshihiro Shimoda <[email protected]>
12+
13+
allOf:
14+
- $ref: snps,dw-pcie-ep.yaml#
15+
16+
properties:
17+
compatible:
18+
items:
19+
- const: renesas,r8a779f0-pcie-ep # R-Car S4-8
20+
- const: renesas,rcar-gen4-pcie-ep # R-Car Gen4
21+
22+
reg:
23+
maxItems: 7
24+
25+
reg-names:
26+
items:
27+
- const: dbi
28+
- const: dbi2
29+
- const: atu
30+
- const: dma
31+
- const: app
32+
- const: phy
33+
- const: addr_space
34+
35+
interrupts:
36+
maxItems: 3
37+
38+
interrupt-names:
39+
items:
40+
- const: dma
41+
- const: sft_ce
42+
- const: app
43+
44+
clocks:
45+
maxItems: 2
46+
47+
clock-names:
48+
items:
49+
- const: core
50+
- const: ref
51+
52+
power-domains:
53+
maxItems: 1
54+
55+
resets:
56+
maxItems: 1
57+
58+
reset-names:
59+
items:
60+
- const: pwr
61+
62+
max-link-speed:
63+
maximum: 4
64+
65+
num-lanes:
66+
maximum: 4
67+
68+
max-functions:
69+
maximum: 2
70+
71+
required:
72+
- compatible
73+
- reg
74+
- reg-names
75+
- interrupts
76+
- interrupt-names
77+
- clocks
78+
- clock-names
79+
- power-domains
80+
- resets
81+
- reset-names
82+
83+
unevaluatedProperties: false
84+
85+
examples:
86+
- |
87+
#include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
88+
#include <dt-bindings/interrupt-controller/arm-gic.h>
89+
#include <dt-bindings/power/r8a779f0-sysc.h>
90+
91+
soc {
92+
#address-cells = <2>;
93+
#size-cells = <2>;
94+
95+
pcie0_ep: pcie-ep@e65d0000 {
96+
compatible = "renesas,r8a779f0-pcie-ep", "renesas,rcar-gen4-pcie-ep";
97+
reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
98+
<0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
99+
<0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
100+
<0 0xfe000000 0 0x400000>;
101+
reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
102+
interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
103+
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
104+
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
105+
interrupt-names = "dma", "sft_ce", "app";
106+
clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
107+
clock-names = "core", "ref";
108+
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
109+
resets = <&cpg 624>;
110+
reset-names = "pwr";
111+
max-link-speed = <4>;
112+
num-lanes = <2>;
113+
max-functions = /bits/ 8 <2>;
114+
};
115+
};

‎Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml

Lines changed: 127 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,127 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
# Copyright (C) 2022-2023 Renesas Electronics Corp.
3+
%YAML 1.2
4+
---
5+
$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-host.yaml#
6+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7+
8+
title: Renesas R-Car Gen4 PCIe Host
9+
10+
maintainers:
11+
- Yoshihiro Shimoda <[email protected]>
12+
13+
allOf:
14+
- $ref: snps,dw-pcie.yaml#
15+
16+
properties:
17+
compatible:
18+
items:
19+
- const: renesas,r8a779f0-pcie # R-Car S4-8
20+
- const: renesas,rcar-gen4-pcie # R-Car Gen4
21+
22+
reg:
23+
maxItems: 7
24+
25+
reg-names:
26+
items:
27+
- const: dbi
28+
- const: dbi2
29+
- const: atu
30+
- const: dma
31+
- const: app
32+
- const: phy
33+
- const: config
34+
35+
interrupts:
36+
maxItems: 4
37+
38+
interrupt-names:
39+
items:
40+
- const: msi
41+
- const: dma
42+
- const: sft_ce
43+
- const: app
44+
45+
clocks:
46+
maxItems: 2
47+
48+
clock-names:
49+
items:
50+
- const: core
51+
- const: ref
52+
53+
power-domains:
54+
maxItems: 1
55+
56+
resets:
57+
maxItems: 1
58+
59+
reset-names:
60+
items:
61+
- const: pwr
62+
63+
max-link-speed:
64+
maximum: 4
65+
66+
num-lanes:
67+
maximum: 4
68+
69+
required:
70+
- compatible
71+
- reg
72+
- reg-names
73+
- interrupts
74+
- interrupt-names
75+
- clocks
76+
- clock-names
77+
- power-domains
78+
- resets
79+
- reset-names
80+
81+
unevaluatedProperties: false
82+
83+
examples:
84+
- |
85+
#include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
86+
#include <dt-bindings/interrupt-controller/arm-gic.h>
87+
#include <dt-bindings/power/r8a779f0-sysc.h>
88+
89+
soc {
90+
#address-cells = <2>;
91+
#size-cells = <2>;
92+
93+
pcie: pcie@e65d0000 {
94+
compatible = "renesas,r8a779f0-pcie", "renesas,rcar-gen4-pcie";
95+
reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
96+
<0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
97+
<0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
98+
<0 0xfe000000 0 0x400000>;
99+
reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
100+
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
101+
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
102+
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
103+
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
104+
interrupt-names = "msi", "dma", "sft_ce", "app";
105+
clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
106+
clock-names = "core", "ref";
107+
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
108+
resets = <&cpg 624>;
109+
reset-names = "pwr";
110+
max-link-speed = <4>;
111+
num-lanes = <2>;
112+
#address-cells = <3>;
113+
#size-cells = <2>;
114+
bus-range = <0x00 0xff>;
115+
device_type = "pci";
116+
ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
117+
<0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
118+
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
119+
#interrupt-cells = <1>;
120+
interrupt-map-mask = <0 0 0 7>;
121+
interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
122+
<0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
123+
<0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
124+
<0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
125+
snps,enable-cdm-check;
126+
};
127+
};

‎Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -33,11 +33,11 @@ properties:
3333
specific for each activated function, while the rest of the sub-spaces
3434
are common for all of them (if there are more than one).
3535
minItems: 2
36-
maxItems: 6
36+
maxItems: 7
3737

3838
reg-names:
3939
minItems: 2
40-
maxItems: 6
40+
maxItems: 7
4141

4242
interrupts:
4343
description:

‎Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -33,11 +33,11 @@ properties:
3333
normal controller functioning. iATU memory IO region is also required
3434
if the space is unrolled (IP-core version >= 4.80a).
3535
minItems: 2
36-
maxItems: 5
36+
maxItems: 7
3737

3838
reg-names:
3939
minItems: 2
40-
maxItems: 5
40+
maxItems: 7
4141
items:
4242
oneOf:
4343
- description:

‎Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -42,11 +42,11 @@ properties:
4242
are required for the normal controller work. iATU memory IO region is
4343
also required if the space is unrolled (IP-core version >= 4.80a).
4444
minItems: 2
45-
maxItems: 5
45+
maxItems: 7
4646

4747
reg-names:
4848
minItems: 2
49-
maxItems: 5
49+
maxItems: 7
5050
items:
5151
oneOf:
5252
- description:

‎Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,7 @@ examples:
118118
compatible = "xlnx,nwl-pcie-2.11";
119119
reg = <0x0 0xfd0e0000 0x0 0x1000>,
120120
<0x0 0xfd480000 0x0 0x1000>,
121-
<0x80 0x00000000 0x0 0x1000000>;
121+
<0x80 0x00000000 0x0 0x10000000>;
122122
reg-names = "breg", "pcireg", "cfg";
123123
ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
124124
<0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>;

0 commit comments

Comments
 (0)