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jeyetam
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gregkh
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Revert "serial/8250: Add support for NI-Serial PXI/PXIe+485 devices"
This reverts commit fdc2de8 ("serial/8250: Add support for NI-Serial PXI/PXIe+485 devices"). The commit fdc2de8 ("serial/8250: Add support for NI-Serial PXI/PXIe+485 devices") introduced a breakage on NI-Serial PXI(e)-RS485 devices, RS-232 variants have no issue. The Linux system can enumerate the NI-Serial PXI(e)-RS485 devices, but it broke the R/W operation on the ports. However, the implementation is working on the NI internal Linux RT kernel but it does not work in the Linux main tree kernel. This is only affecting NI products, specifically the RS-485 variants. Reverting the upstream until a proper implementation that can apply to both NI internal Linux kernel and Linux mainline kernel is figured out. Signed-off-by: Je Yen Tam <[email protected]> Fixes: fdc2de8 ("serial/8250: Add support for NI-Serial PXI/PXIe+485 devices") Cc: stable <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
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‎drivers/tty/serial/8250/8250_pci.c

Lines changed: 4 additions & 288 deletions
Original file line numberDiff line numberDiff line change
@@ -745,16 +745,8 @@ static int pci_ni8430_init(struct pci_dev *dev)
745745
}
746746

747747
/* UART Port Control Register */
748-
#define NI16550_PCR_OFFSET 0x0f
749-
#define NI16550_PCR_RS422 0x00
750-
#define NI16550_PCR_ECHO_RS485 0x01
751-
#define NI16550_PCR_DTR_RS485 0x02
752-
#define NI16550_PCR_AUTO_RS485 0x03
753-
#define NI16550_PCR_WIRE_MODE_MASK 0x03
754-
#define NI16550_PCR_TXVR_ENABLE_BIT BIT(3)
755-
#define NI16550_PCR_RS485_TERMINATION_BIT BIT(6)
756-
#define NI16550_ACR_DTR_AUTO_DTR (0x2 << 3)
757-
#define NI16550_ACR_DTR_MANUAL_DTR (0x0 << 3)
748+
#define NI8430_PORTCON 0x0f
749+
#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
758750

759751
static int
760752
pci_ni8430_setup(struct serial_private *priv,
@@ -776,117 +768,14 @@ pci_ni8430_setup(struct serial_private *priv,
776768
return -ENOMEM;
777769

778770
/* enable the transceiver */
779-
writeb(readb(p + offset + NI16550_PCR_OFFSET) | NI16550_PCR_TXVR_ENABLE_BIT,
780-
p + offset + NI16550_PCR_OFFSET);
771+
writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
772+
p + offset + NI8430_PORTCON);
781773

782774
iounmap(p);
783775

784776
return setup_port(priv, port, bar, offset, board->reg_shift);
785777
}
786778

787-
static int pci_ni8431_config_rs485(struct uart_port *port,
788-
struct serial_rs485 *rs485)
789-
{
790-
u8 pcr, acr;
791-
struct uart_8250_port *up;
792-
793-
up = container_of(port, struct uart_8250_port, port);
794-
acr = up->acr;
795-
pcr = port->serial_in(port, NI16550_PCR_OFFSET);
796-
pcr &= ~NI16550_PCR_WIRE_MODE_MASK;
797-
798-
if (rs485->flags & SER_RS485_ENABLED) {
799-
/* RS-485 */
800-
if ((rs485->flags & SER_RS485_RX_DURING_TX) &&
801-
(rs485->flags & SER_RS485_RTS_ON_SEND)) {
802-
dev_dbg(port->dev, "Invalid 2-wire mode\n");
803-
return -EINVAL;
804-
}
805-
806-
if (rs485->flags & SER_RS485_RX_DURING_TX) {
807-
/* Echo */
808-
dev_vdbg(port->dev, "2-wire DTR with echo\n");
809-
pcr |= NI16550_PCR_ECHO_RS485;
810-
acr |= NI16550_ACR_DTR_MANUAL_DTR;
811-
} else {
812-
/* Auto or DTR */
813-
if (rs485->flags & SER_RS485_RTS_ON_SEND) {
814-
/* Auto */
815-
dev_vdbg(port->dev, "2-wire Auto\n");
816-
pcr |= NI16550_PCR_AUTO_RS485;
817-
acr |= NI16550_ACR_DTR_AUTO_DTR;
818-
} else {
819-
/* DTR-controlled */
820-
/* No Echo */
821-
dev_vdbg(port->dev, "2-wire DTR no echo\n");
822-
pcr |= NI16550_PCR_DTR_RS485;
823-
acr |= NI16550_ACR_DTR_MANUAL_DTR;
824-
}
825-
}
826-
} else {
827-
/* RS-422 */
828-
dev_vdbg(port->dev, "4-wire\n");
829-
pcr |= NI16550_PCR_RS422;
830-
acr |= NI16550_ACR_DTR_MANUAL_DTR;
831-
}
832-
833-
dev_dbg(port->dev, "write pcr: 0x%08x\n", pcr);
834-
port->serial_out(port, NI16550_PCR_OFFSET, pcr);
835-
836-
up->acr = acr;
837-
port->serial_out(port, UART_SCR, UART_ACR);
838-
port->serial_out(port, UART_ICR, up->acr);
839-
840-
/* Update the cache. */
841-
port->rs485 = *rs485;
842-
843-
return 0;
844-
}
845-
846-
static int pci_ni8431_setup(struct serial_private *priv,
847-
const struct pciserial_board *board,
848-
struct uart_8250_port *uart, int idx)
849-
{
850-
u8 pcr, acr;
851-
struct pci_dev *dev = priv->dev;
852-
void __iomem *addr;
853-
unsigned int bar, offset = board->first_offset;
854-
855-
if (idx >= board->num_ports)
856-
return 1;
857-
858-
bar = FL_GET_BASE(board->flags);
859-
offset += idx * board->uart_offset;
860-
861-
addr = pci_ioremap_bar(dev, bar);
862-
if (!addr)
863-
return -ENOMEM;
864-
865-
/* enable the transceiver */
866-
writeb(readb(addr + NI16550_PCR_OFFSET) | NI16550_PCR_TXVR_ENABLE_BIT,
867-
addr + NI16550_PCR_OFFSET);
868-
869-
pcr = readb(addr + NI16550_PCR_OFFSET);
870-
pcr &= ~NI16550_PCR_WIRE_MODE_MASK;
871-
872-
/* set wire mode to default RS-422 */
873-
pcr |= NI16550_PCR_RS422;
874-
acr = NI16550_ACR_DTR_MANUAL_DTR;
875-
876-
/* write port configuration to register */
877-
writeb(pcr, addr + NI16550_PCR_OFFSET);
878-
879-
/* access and write to UART acr register */
880-
writeb(UART_ACR, addr + UART_SCR);
881-
writeb(acr, addr + UART_ICR);
882-
883-
uart->port.rs485_config = &pci_ni8431_config_rs485;
884-
885-
iounmap(addr);
886-
887-
return setup_port(priv, uart, bar, offset, board->reg_shift);
888-
}
889-
890779
static int pci_netmos_9900_setup(struct serial_private *priv,
891780
const struct pciserial_board *board,
892781
struct uart_8250_port *port, int idx)
@@ -2023,15 +1912,6 @@ pci_moxa_setup(struct serial_private *priv,
20231912
#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9
20241913
#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
20251914

2026-
#define PCIE_DEVICE_ID_NI_PXIE8430_2328 0x74C2
2027-
#define PCIE_DEVICE_ID_NI_PXIE8430_23216 0x74C1
2028-
#define PCI_DEVICE_ID_NI_PXI8431_4852 0x7081
2029-
#define PCI_DEVICE_ID_NI_PXI8431_4854 0x70DE
2030-
#define PCI_DEVICE_ID_NI_PXI8431_4858 0x70E3
2031-
#define PCI_DEVICE_ID_NI_PXI8433_4852 0x70E9
2032-
#define PCI_DEVICE_ID_NI_PXI8433_4854 0x70ED
2033-
#define PCIE_DEVICE_ID_NI_PXIE8431_4858 0x74C4
2034-
#define PCIE_DEVICE_ID_NI_PXIE8431_48516 0x74C3
20351915

20361916
#define PCI_DEVICE_ID_MOXA_CP102E 0x1024
20371917
#define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
@@ -2269,87 +2149,6 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
22692149
.setup = pci_ni8430_setup,
22702150
.exit = pci_ni8430_exit,
22712151
},
2272-
{
2273-
.vendor = PCI_VENDOR_ID_NI,
2274-
.device = PCIE_DEVICE_ID_NI_PXIE8430_2328,
2275-
.subvendor = PCI_ANY_ID,
2276-
.subdevice = PCI_ANY_ID,
2277-
.init = pci_ni8430_init,
2278-
.setup = pci_ni8430_setup,
2279-
.exit = pci_ni8430_exit,
2280-
},
2281-
{
2282-
.vendor = PCI_VENDOR_ID_NI,
2283-
.device = PCIE_DEVICE_ID_NI_PXIE8430_23216,
2284-
.subvendor = PCI_ANY_ID,
2285-
.subdevice = PCI_ANY_ID,
2286-
.init = pci_ni8430_init,
2287-
.setup = pci_ni8430_setup,
2288-
.exit = pci_ni8430_exit,
2289-
},
2290-
{
2291-
.vendor = PCI_VENDOR_ID_NI,
2292-
.device = PCI_DEVICE_ID_NI_PXI8431_4852,
2293-
.subvendor = PCI_ANY_ID,
2294-
.subdevice = PCI_ANY_ID,
2295-
.init = pci_ni8430_init,
2296-
.setup = pci_ni8431_setup,
2297-
.exit = pci_ni8430_exit,
2298-
},
2299-
{
2300-
.vendor = PCI_VENDOR_ID_NI,
2301-
.device = PCI_DEVICE_ID_NI_PXI8431_4854,
2302-
.subvendor = PCI_ANY_ID,
2303-
.subdevice = PCI_ANY_ID,
2304-
.init = pci_ni8430_init,
2305-
.setup = pci_ni8431_setup,
2306-
.exit = pci_ni8430_exit,
2307-
},
2308-
{
2309-
.vendor = PCI_VENDOR_ID_NI,
2310-
.device = PCI_DEVICE_ID_NI_PXI8431_4858,
2311-
.subvendor = PCI_ANY_ID,
2312-
.subdevice = PCI_ANY_ID,
2313-
.init = pci_ni8430_init,
2314-
.setup = pci_ni8431_setup,
2315-
.exit = pci_ni8430_exit,
2316-
},
2317-
{
2318-
.vendor = PCI_VENDOR_ID_NI,
2319-
.device = PCI_DEVICE_ID_NI_PXI8433_4852,
2320-
.subvendor = PCI_ANY_ID,
2321-
.subdevice = PCI_ANY_ID,
2322-
.init = pci_ni8430_init,
2323-
.setup = pci_ni8431_setup,
2324-
.exit = pci_ni8430_exit,
2325-
},
2326-
{
2327-
.vendor = PCI_VENDOR_ID_NI,
2328-
.device = PCI_DEVICE_ID_NI_PXI8433_4854,
2329-
.subvendor = PCI_ANY_ID,
2330-
.subdevice = PCI_ANY_ID,
2331-
.init = pci_ni8430_init,
2332-
.setup = pci_ni8431_setup,
2333-
.exit = pci_ni8430_exit,
2334-
},
2335-
{
2336-
.vendor = PCI_VENDOR_ID_NI,
2337-
.device = PCIE_DEVICE_ID_NI_PXIE8431_4858,
2338-
.subvendor = PCI_ANY_ID,
2339-
.subdevice = PCI_ANY_ID,
2340-
.init = pci_ni8430_init,
2341-
.setup = pci_ni8431_setup,
2342-
.exit = pci_ni8430_exit,
2343-
},
2344-
{
2345-
.vendor = PCI_VENDOR_ID_NI,
2346-
.device = PCIE_DEVICE_ID_NI_PXIE8431_48516,
2347-
.subvendor = PCI_ANY_ID,
2348-
.subdevice = PCI_ANY_ID,
2349-
.init = pci_ni8430_init,
2350-
.setup = pci_ni8431_setup,
2351-
.exit = pci_ni8430_exit,
2352-
},
23532152
/* Quatech */
23542153
{
23552154
.vendor = PCI_VENDOR_ID_QUATECH,
@@ -3106,13 +2905,6 @@ enum pci_board_num_t {
31062905
pbn_ni8430_4,
31072906
pbn_ni8430_8,
31082907
pbn_ni8430_16,
3109-
pbn_ni8430_pxie_8,
3110-
pbn_ni8430_pxie_16,
3111-
pbn_ni8431_2,
3112-
pbn_ni8431_4,
3113-
pbn_ni8431_8,
3114-
pbn_ni8431_pxie_8,
3115-
pbn_ni8431_pxie_16,
31162908
pbn_ADDIDATA_PCIe_1_3906250,
31172909
pbn_ADDIDATA_PCIe_2_3906250,
31182910
pbn_ADDIDATA_PCIe_4_3906250,
@@ -3765,55 +3557,6 @@ static struct pciserial_board pci_boards[] = {
37653557
.uart_offset = 0x10,
37663558
.first_offset = 0x800,
37673559
},
3768-
[pbn_ni8430_pxie_16] = {
3769-
.flags = FL_BASE0,
3770-
.num_ports = 16,
3771-
.base_baud = 3125000,
3772-
.uart_offset = 0x10,
3773-
.first_offset = 0x800,
3774-
},
3775-
[pbn_ni8430_pxie_8] = {
3776-
.flags = FL_BASE0,
3777-
.num_ports = 8,
3778-
.base_baud = 3125000,
3779-
.uart_offset = 0x10,
3780-
.first_offset = 0x800,
3781-
},
3782-
[pbn_ni8431_8] = {
3783-
.flags = FL_BASE0,
3784-
.num_ports = 8,
3785-
.base_baud = 3686400,
3786-
.uart_offset = 0x10,
3787-
.first_offset = 0x800,
3788-
},
3789-
[pbn_ni8431_4] = {
3790-
.flags = FL_BASE0,
3791-
.num_ports = 4,
3792-
.base_baud = 3686400,
3793-
.uart_offset = 0x10,
3794-
.first_offset = 0x800,
3795-
},
3796-
[pbn_ni8431_2] = {
3797-
.flags = FL_BASE0,
3798-
.num_ports = 2,
3799-
.base_baud = 3686400,
3800-
.uart_offset = 0x10,
3801-
.first_offset = 0x800,
3802-
},
3803-
[pbn_ni8431_pxie_16] = {
3804-
.flags = FL_BASE0,
3805-
.num_ports = 16,
3806-
.base_baud = 3125000,
3807-
.uart_offset = 0x10,
3808-
.first_offset = 0x800,
3809-
},
3810-
[pbn_ni8431_pxie_8] = {
3811-
.flags = FL_BASE0,
3812-
.num_ports = 8,
3813-
.base_baud = 3125000,
3814-
.uart_offset = 0x10,
3815-
.first_offset = 0x800,
3816-
},
38173560
/*
38183561
* ADDI-DATA GmbH PCI-Express communication cards <[email protected]>
38193562
*/
@@ -5567,33 +5310,6 @@ static const struct pci_device_id serial_pci_tbl[] = {
55675310
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
55685311
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
55695312
pbn_ni8430_4 },
5570-
{ PCI_VENDOR_ID_NI, PCIE_DEVICE_ID_NI_PXIE8430_2328,
5571-
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5572-
pbn_ni8430_pxie_8 },
5573-
{ PCI_VENDOR_ID_NI, PCIE_DEVICE_ID_NI_PXIE8430_23216,
5574-
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5575-
pbn_ni8430_pxie_16 },
5576-
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8431_4852,
5577-
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5578-
pbn_ni8431_2 },
5579-
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8431_4854,
5580-
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5581-
pbn_ni8431_4 },
5582-
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8431_4858,
5583-
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5584-
pbn_ni8431_8 },
5585-
{ PCI_VENDOR_ID_NI, PCIE_DEVICE_ID_NI_PXIE8431_4858,
5586-
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5587-
pbn_ni8431_pxie_8 },
5588-
{ PCI_VENDOR_ID_NI, PCIE_DEVICE_ID_NI_PXIE8431_48516,
5589-
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5590-
pbn_ni8431_pxie_16 },
5591-
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8433_4852,
5592-
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5593-
pbn_ni8431_2 },
5594-
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8433_4854,
5595-
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5596-
pbn_ni8431_4 },
55975313

55985314
/*
55995315
* MOXA

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