Skip to content

Commit 2865463

Browse files
ouptonoupton
committed
Merge branch kvm-arm64/nv-s1pie-s1poe into kvmarm/next
* kvm-arm64/nv-s1pie-s1poe: (36 commits) : NV support for S1PIE/S1POE, courtesy of Marc Zyngier : : Complete support for S1PIE/S1POE at vEL2, including: : : - Save/restore of the vEL2 sysreg context : : - Use the S1PIE/S1POE context for fast-path AT emulation : : - Enlightening the software walker to the behavior of S1PIE/S1POE : : - Like any other good NV series, some trap routing descriptions KVM: arm64: Handle WXN attribute KVM: arm64: Handle stage-1 permission overlays KVM: arm64: Make PAN conditions part of the S1 walk context KVM: arm64: Disable hierarchical permissions when POE is enabled KVM: arm64: Add POE save/restore for AT emulation fast-path KVM: arm64: Add save/restore support for POR_EL2 KVM: arm64: Add basic support for POR_EL2 KVM: arm64: Add kvm_has_s1poe() helper KVM: arm64: Subject S1PIE/S1POE registers to HCR_EL2.{TVM,TRVM} KVM: arm64: Drop bogus CPTR_EL2.E0POE trap routing arm64: Add encoding for POR_EL2 KVM: arm64: Rely on visibility to let PIR*_ELx/TCR2_ELx UNDEF KVM: arm64: Hide S1PIE registers from userspace when disabled for guests KVM: arm64: Hide TCR2_EL1 from userspace when disabled for guests KVM: arm64: Define helper for EL2 registers with custom visibility KVM: arm64: Add a composite EL2 visibility helper KVM: arm64: Implement AT S1PIE support KVM: arm64: Disable hierarchical permissions when S1PIE is enabled KVM: arm64: Split S1 permission evaluation into direct and hierarchical parts KVM: arm64: Add AT fast-path support for S1PIE ... Signed-off-by: Oliver Upton <[email protected]>
2 parents 8198375 + 1c6801d commit 2865463

File tree

11 files changed

+771
-118
lines changed

11 files changed

+771
-118
lines changed

‎arch/arm64/include/asm/kvm_host.h

Lines changed: 34 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -374,7 +374,7 @@ struct kvm_arch {
374374

375375
u64 ctr_el0;
376376

377-
/* Masks for VNCR-baked sysregs */
377+
/* Masks for VNCR-backed and general EL2 sysregs */
378378
struct kvm_sysreg_masks *sysreg_masks;
379379

380380
/*
@@ -408,6 +408,9 @@ struct kvm_vcpu_fault_info {
408408
r = __VNCR_START__ + ((VNCR_ ## r) / 8), \
409409
__after_##r = __MAX__(__before_##r - 1, r)
410410

411+
#define MARKER(m) \
412+
m, __after_##m = m - 1
413+
411414
enum vcpu_sysreg {
412415
__INVALID_SYSREG__, /* 0 is reserved as an invalid value */
413416
MPIDR_EL1, /* MultiProcessor Affinity Register */
@@ -475,6 +478,9 @@ enum vcpu_sysreg {
475478
TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */
476479
TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */
477480
TCR_EL2, /* Translation Control Register (EL2) */
481+
PIRE0_EL2, /* Permission Indirection Register 0 (EL2) */
482+
PIR_EL2, /* Permission Indirection Register 1 (EL2) */
483+
POR_EL2, /* Permission Overlay Register 2 (EL2) */
478484
SPSR_EL2, /* EL2 saved program status register */
479485
ELR_EL2, /* EL2 exception link register */
480486
AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */
@@ -494,7 +500,12 @@ enum vcpu_sysreg {
494500
CNTHV_CTL_EL2,
495501
CNTHV_CVAL_EL2,
496502

497-
__VNCR_START__, /* Any VNCR-capable reg goes after this point */
503+
/* Anything from this can be RES0/RES1 sanitised */
504+
MARKER(__SANITISED_REG_START__),
505+
TCR2_EL2, /* Extended Translation Control Register (EL2) */
506+
507+
/* Any VNCR-capable reg goes after this point */
508+
MARKER(__VNCR_START__),
498509

499510
VNCR(SCTLR_EL1),/* System Control Register */
500511
VNCR(ACTLR_EL1),/* Auxiliary Control Register */
@@ -554,7 +565,7 @@ struct kvm_sysreg_masks {
554565
struct {
555566
u64 res0;
556567
u64 res1;
557-
} mask[NR_SYS_REGS - __VNCR_START__];
568+
} mask[NR_SYS_REGS - __SANITISED_REG_START__];
558569
};
559570

560571
struct kvm_cpu_context {
@@ -1002,13 +1013,13 @@ static inline u64 *___ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r)
10021013

10031014
#define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r))
10041015

1005-
u64 kvm_vcpu_sanitise_vncr_reg(const struct kvm_vcpu *, enum vcpu_sysreg);
1016+
u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *, enum vcpu_sysreg, u64);
10061017
#define __vcpu_sys_reg(v,r) \
10071018
(*({ \
10081019
const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \
10091020
u64 *__r = __ctxt_sys_reg(ctxt, (r)); \
1010-
if (vcpu_has_nv((v)) && (r) >= __VNCR_START__) \
1011-
*__r = kvm_vcpu_sanitise_vncr_reg((v), (r)); \
1021+
if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \
1022+
*__r = kvm_vcpu_apply_reg_masks((v), (r), *__r);\
10121023
__r; \
10131024
}))
10141025

@@ -1037,6 +1048,10 @@ static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
10371048
case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break;
10381049
case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break;
10391050
case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break;
1051+
case TCR2_EL1: *val = read_sysreg_s(SYS_TCR2_EL12); break;
1052+
case PIR_EL1: *val = read_sysreg_s(SYS_PIR_EL12); break;
1053+
case PIRE0_EL1: *val = read_sysreg_s(SYS_PIRE0_EL12); break;
1054+
case POR_EL1: *val = read_sysreg_s(SYS_POR_EL12); break;
10401055
case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break;
10411056
case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break;
10421057
case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break;
@@ -1083,6 +1098,10 @@ static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
10831098
case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break;
10841099
case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break;
10851100
case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break;
1101+
case TCR2_EL1: write_sysreg_s(val, SYS_TCR2_EL12); break;
1102+
case PIR_EL1: write_sysreg_s(val, SYS_PIR_EL12); break;
1103+
case PIRE0_EL1: write_sysreg_s(val, SYS_PIRE0_EL12); break;
1104+
case POR_EL1: write_sysreg_s(val, SYS_POR_EL12); break;
10861105
case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
10871106
case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
10881107
case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
@@ -1503,4 +1522,13 @@ void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val);
15031522
(system_supports_fpmr() && \
15041523
kvm_has_feat((k), ID_AA64PFR2_EL1, FPMR, IMP))
15051524

1525+
#define kvm_has_tcr2(k) \
1526+
(kvm_has_feat((k), ID_AA64MMFR3_EL1, TCRX, IMP))
1527+
1528+
#define kvm_has_s1pie(k) \
1529+
(kvm_has_feat((k), ID_AA64MMFR3_EL1, S1PIE, IMP))
1530+
1531+
#define kvm_has_s1poe(k) \
1532+
(kvm_has_feat((k), ID_AA64MMFR3_EL1, S1POE, IMP))
1533+
15061534
#endif /* __ARM64_KVM_HOST_H__ */

‎arch/arm64/include/asm/vncr_mapping.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,6 @@
5050
#define VNCR_VBAR_EL1 0x250
5151
#define VNCR_TCR2_EL1 0x270
5252
#define VNCR_PIRE0_EL1 0x290
53-
#define VNCR_PIRE0_EL2 0x298
5453
#define VNCR_PIR_EL1 0x2A0
5554
#define VNCR_POR_EL1 0x2A8
5655
#define VNCR_ICH_LR0_EL2 0x400

0 commit comments

Comments
 (0)