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#define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2)
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#define LVTS_HW_SHUTDOWN_MT7988 105000
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+ #define LVTS_HW_SHUTDOWN_MT8192 105000
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#define LVTS_HW_SHUTDOWN_MT8195 105000
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#define LVTS_MINIMUM_THRESHOLD 20000
@@ -1329,6 +1330,88 @@ static int lvts_resume(struct device *dev)
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return 0 ;
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}
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+ static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl [] = {
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+ {
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+ .cal_offset = { 0x04 , 0x08 },
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+ .lvts_sensor = {
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+ { .dt_id = MT8192_MCU_BIG_CPU0 },
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+ { .dt_id = MT8192_MCU_BIG_CPU1 }
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+ },
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+ .num_lvts_sensor = 2 ,
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+ .offset = 0x0 ,
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+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192 ,
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+ .mode = LVTS_MSR_FILTERED_MODE ,
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+ },
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+ {
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+ .cal_offset = { 0x0c , 0x10 },
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+ .lvts_sensor = {
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+ { .dt_id = MT8192_MCU_BIG_CPU2 },
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+ { .dt_id = MT8192_MCU_BIG_CPU3 }
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+ },
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+ .num_lvts_sensor = 2 ,
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+ .offset = 0x100 ,
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+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192 ,
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+ .mode = LVTS_MSR_FILTERED_MODE ,
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+ },
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+ {
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+ .cal_offset = { 0x14 , 0x18 , 0x1c , 0x20 },
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+ .lvts_sensor = {
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+ { .dt_id = MT8192_MCU_LITTLE_CPU0 },
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+ { .dt_id = MT8192_MCU_LITTLE_CPU1 },
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+ { .dt_id = MT8192_MCU_LITTLE_CPU2 },
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+ { .dt_id = MT8192_MCU_LITTLE_CPU3 }
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+ },
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+ .num_lvts_sensor = 4 ,
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+ .offset = 0x200 ,
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+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192 ,
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+ .mode = LVTS_MSR_FILTERED_MODE ,
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+ }
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+ };
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+
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+ static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl [] = {
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+ {
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+ .cal_offset = { 0x24 , 0x28 },
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+ .lvts_sensor = {
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+ { .dt_id = MT8192_AP_VPU0 },
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+ { .dt_id = MT8192_AP_VPU1 }
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+ },
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+ .num_lvts_sensor = 2 ,
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+ .offset = 0x0 ,
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+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192 ,
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+ },
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+ {
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+ .cal_offset = { 0x2c , 0x30 },
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+ .lvts_sensor = {
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+ { .dt_id = MT8192_AP_GPU0 },
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+ { .dt_id = MT8192_AP_GPU1 }
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+ },
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+ .num_lvts_sensor = 2 ,
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+ .offset = 0x100 ,
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+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192 ,
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+ },
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+ {
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+ .cal_offset = { 0x34 , 0x38 },
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+ .lvts_sensor = {
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+ { .dt_id = MT8192_AP_INFRA },
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+ { .dt_id = MT8192_AP_CAM },
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+ },
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+ .num_lvts_sensor = 2 ,
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+ .offset = 0x200 ,
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+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192 ,
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+ },
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+ {
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+ .cal_offset = { 0x3c , 0x40 , 0x44 },
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+ .lvts_sensor = {
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+ { .dt_id = MT8192_AP_MD0 },
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+ { .dt_id = MT8192_AP_MD1 },
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+ { .dt_id = MT8192_AP_MD2 }
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+ },
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+ .num_lvts_sensor = 3 ,
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+ .offset = 0x300 ,
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+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192 ,
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+ }
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+ };
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+
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static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl [] = {
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{
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.cal_offset = { 0x04 , 0x07 },
@@ -1415,6 +1498,16 @@ static const struct lvts_data mt7988_lvts_ap_data = {
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.temp_offset = LVTS_COEFF_B_MT7988 ,
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};
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+ static const struct lvts_data mt8192_lvts_mcu_data = {
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+ .lvts_ctrl = mt8192_lvts_mcu_data_ctrl ,
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+ .num_lvts_ctrl = ARRAY_SIZE (mt8192_lvts_mcu_data_ctrl ),
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+ };
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+
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+ static const struct lvts_data mt8192_lvts_ap_data = {
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+ .lvts_ctrl = mt8192_lvts_ap_data_ctrl ,
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+ .num_lvts_ctrl = ARRAY_SIZE (mt8192_lvts_ap_data_ctrl ),
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+ };
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+
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static const struct lvts_data mt8195_lvts_mcu_data = {
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.lvts_ctrl = mt8195_lvts_mcu_data_ctrl ,
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.num_lvts_ctrl = ARRAY_SIZE (mt8195_lvts_mcu_data_ctrl ),
@@ -1431,6 +1524,8 @@ static const struct lvts_data mt8195_lvts_ap_data = {
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static const struct of_device_id lvts_of_match [] = {
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{ .compatible = "mediatek,mt7988-lvts-ap" , .data = & mt7988_lvts_ap_data },
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+ { .compatible = "mediatek,mt8192-lvts-mcu" , .data = & mt8192_lvts_mcu_data },
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+ { .compatible = "mediatek,mt8192-lvts-ap" , .data = & mt8192_lvts_ap_data },
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{ .compatible = "mediatek,mt8195-lvts-mcu" , .data = & mt8195_lvts_mcu_data },
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{ .compatible = "mediatek,mt8195-lvts-ap" , .data = & mt8195_lvts_ap_data },
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{},
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