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Merge branch 'net-stmmac-dwmac-rk-add-gmac-support-for-rk3528'
Jonas Karlman says: ==================== net: stmmac: dwmac-rk: Add GMAC support for RK3528 The Rockchip RK3528 has two Ethernet controllers, one 100/10 MAC to be used with the integrated PHY and a second 1000/100/10 MAC to be used with an external Ethernet PHY. This series add initial support for the Ethernet controllers found in RK3528 and initial support to power up/down the integrated PHY. v2: https://lore.kernel.org/[email protected] v1: https://lore.kernel.org/[email protected] ==================== Link: https://patch.msgid.link/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2 parents 73ed6f5 + 83e7b35 commit 28d47bc

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‎Documentation/devicetree/bindings/net/rockchip-dwmac.yaml

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@ select:
2424
- rockchip,rk3366-gmac
2525
- rockchip,rk3368-gmac
2626
- rockchip,rk3399-gmac
27+
- rockchip,rk3528-gmac
2728
- rockchip,rk3568-gmac
2829
- rockchip,rk3576-gmac
2930
- rockchip,rk3588-gmac
@@ -49,6 +50,7 @@ properties:
4950
- rockchip,rv1108-gmac
5051
- items:
5152
- enum:
53+
- rockchip,rk3528-gmac
5254
- rockchip,rk3568-gmac
5355
- rockchip,rk3576-gmac
5456
- rockchip,rk3588-gmac
@@ -66,7 +68,7 @@ properties:
6668
- const: eth_wake_irq
6769

6870
clocks:
69-
minItems: 5
71+
minItems: 4
7072
maxItems: 8
7173

7274
clock-names:
@@ -140,6 +142,18 @@ allOf:
140142
properties:
141143
rockchip,php-grf: false
142144

145+
- if:
146+
not:
147+
properties:
148+
compatible:
149+
contains:
150+
enum:
151+
- rockchip,rk3528-gmac
152+
then:
153+
properties:
154+
clocks:
155+
minItems: 5
156+
143157
unevaluatedProperties: false
144158

145159
examples:

‎drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c

Lines changed: 227 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@ struct rk_gmac_ops {
3333
void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,
3434
bool enable);
3535
void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
36+
void (*integrated_phy_powerdown)(struct rk_priv_data *bsp_priv);
3637
bool php_grf_required;
3738
bool regs_valid;
3839
u32 regs[];
@@ -92,6 +93,76 @@ struct rk_priv_data {
9293
(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
9394
((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
9495

96+
#define RK_GRF_MACPHY_CON0 0xb00
97+
#define RK_GRF_MACPHY_CON1 0xb04
98+
#define RK_GRF_MACPHY_CON2 0xb08
99+
#define RK_GRF_MACPHY_CON3 0xb0c
100+
101+
#define RK_MACPHY_ENABLE GRF_BIT(0)
102+
#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
103+
#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
104+
#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
105+
#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
106+
#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
107+
108+
static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv)
109+
{
110+
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
111+
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
112+
113+
regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
114+
regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
115+
116+
if (priv->phy_reset) {
117+
/* PHY needs to be disabled before trying to reset it */
118+
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
119+
if (priv->phy_reset)
120+
reset_control_assert(priv->phy_reset);
121+
usleep_range(10, 20);
122+
if (priv->phy_reset)
123+
reset_control_deassert(priv->phy_reset);
124+
usleep_range(10, 20);
125+
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
126+
msleep(30);
127+
}
128+
}
129+
130+
static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv)
131+
{
132+
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
133+
if (priv->phy_reset)
134+
reset_control_assert(priv->phy_reset);
135+
}
136+
137+
#define RK_FEPHY_SHUTDOWN GRF_BIT(1)
138+
#define RK_FEPHY_POWERUP GRF_CLR_BIT(1)
139+
#define RK_FEPHY_INTERNAL_RMII_SEL GRF_BIT(6)
140+
#define RK_FEPHY_24M_CLK_SEL (GRF_BIT(8) | GRF_BIT(9))
141+
#define RK_FEPHY_PHY_ID GRF_BIT(11)
142+
143+
static void rk_gmac_integrated_fephy_powerup(struct rk_priv_data *priv,
144+
unsigned int reg)
145+
{
146+
reset_control_assert(priv->phy_reset);
147+
usleep_range(20, 30);
148+
149+
regmap_write(priv->grf, reg,
150+
RK_FEPHY_POWERUP |
151+
RK_FEPHY_INTERNAL_RMII_SEL |
152+
RK_FEPHY_24M_CLK_SEL |
153+
RK_FEPHY_PHY_ID);
154+
usleep_range(10000, 12000);
155+
156+
reset_control_deassert(priv->phy_reset);
157+
usleep_range(50000, 60000);
158+
}
159+
160+
static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv,
161+
unsigned int reg)
162+
{
163+
regmap_write(priv->grf, reg, RK_FEPHY_SHUTDOWN);
164+
}
165+
95166
#define PX30_GRF_GMAC_CON1 0x0904
96167

97168
/* PX30_GRF_GMAC_CON1 */
@@ -324,14 +395,17 @@ static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
324395
{
325396
regmap_write(priv->grf, RK3228_GRF_CON_MUX,
326397
RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
398+
399+
rk_gmac_integrated_ephy_powerup(priv);
327400
}
328401

329402
static const struct rk_gmac_ops rk3228_ops = {
330403
.set_to_rgmii = rk3228_set_to_rgmii,
331404
.set_to_rmii = rk3228_set_to_rmii,
332405
.set_rgmii_speed = rk3228_set_rgmii_speed,
333406
.set_rmii_speed = rk3228_set_rmii_speed,
334-
.integrated_phy_powerup = rk3228_integrated_phy_powerup,
407+
.integrated_phy_powerup = rk3228_integrated_phy_powerup,
408+
.integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
335409
};
336410

337411
#define RK3288_GRF_SOC_CON1 0x0248
@@ -557,14 +631,17 @@ static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
557631
{
558632
regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
559633
RK3328_MACPHY_RMII_MODE);
634+
635+
rk_gmac_integrated_ephy_powerup(priv);
560636
}
561637

562638
static const struct rk_gmac_ops rk3328_ops = {
563639
.set_to_rgmii = rk3328_set_to_rgmii,
564640
.set_to_rmii = rk3328_set_to_rmii,
565641
.set_rgmii_speed = rk3328_set_rgmii_speed,
566642
.set_rmii_speed = rk3328_set_rmii_speed,
567-
.integrated_phy_powerup = rk3328_integrated_phy_powerup,
643+
.integrated_phy_powerup = rk3328_integrated_phy_powerup,
644+
.integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
568645
};
569646

570647
#define RK3366_GRF_SOC_CON6 0x0418
@@ -828,6 +905,149 @@ static const struct rk_gmac_ops rk3399_ops = {
828905
.set_rmii_speed = rk3399_set_rmii_speed,
829906
};
830907

908+
#define RK3528_VO_GRF_GMAC_CON 0x0018
909+
#define RK3528_VO_GRF_MACPHY_CON0 0x001c
910+
#define RK3528_VO_GRF_MACPHY_CON1 0x0020
911+
#define RK3528_VPU_GRF_GMAC_CON5 0x0018
912+
#define RK3528_VPU_GRF_GMAC_CON6 0x001c
913+
914+
#define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
915+
#define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
916+
#define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
917+
#define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
918+
919+
#define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
920+
#define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
921+
922+
#define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1)
923+
#define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8)
924+
#define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8)
925+
926+
#define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12)
927+
#define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12)
928+
929+
#define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3)
930+
#define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3)
931+
#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10)
932+
#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10)
933+
934+
#define RK3528_GMAC1_CLK_RGMII_DIV1 (GRF_CLR_BIT(11) | GRF_CLR_BIT(10))
935+
#define RK3528_GMAC1_CLK_RGMII_DIV5 (GRF_BIT(11) | GRF_BIT(10))
936+
#define RK3528_GMAC1_CLK_RGMII_DIV50 (GRF_BIT(11) | GRF_CLR_BIT(10))
937+
938+
#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2)
939+
#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2)
940+
#define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9)
941+
#define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9)
942+
943+
static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
944+
int tx_delay, int rx_delay)
945+
{
946+
regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
947+
RK3528_GMAC1_PHY_INTF_SEL_RGMII);
948+
949+
regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
950+
DELAY_ENABLE(RK3528, tx_delay, rx_delay));
951+
952+
regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6,
953+
RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) |
954+
RK3528_GMAC_CLK_TX_DL_CFG(tx_delay));
955+
}
956+
957+
static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
958+
{
959+
if (bsp_priv->id == 1)
960+
regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
961+
RK3528_GMAC1_PHY_INTF_SEL_RMII);
962+
else
963+
regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON,
964+
RK3528_GMAC0_PHY_INTF_SEL_RMII |
965+
RK3528_GMAC0_CLK_RMII_DIV2);
966+
}
967+
968+
static void rk3528_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
969+
{
970+
struct device *dev = &bsp_priv->pdev->dev;
971+
972+
if (speed == 10)
973+
regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
974+
RK3528_GMAC1_CLK_RGMII_DIV50);
975+
else if (speed == 100)
976+
regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
977+
RK3528_GMAC1_CLK_RGMII_DIV5);
978+
else if (speed == 1000)
979+
regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
980+
RK3528_GMAC1_CLK_RGMII_DIV1);
981+
else
982+
dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
983+
}
984+
985+
static void rk3528_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
986+
{
987+
struct device *dev = &bsp_priv->pdev->dev;
988+
unsigned int reg, val;
989+
990+
if (speed == 10)
991+
val = bsp_priv->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV20 :
992+
RK3528_GMAC0_CLK_RMII_DIV20;
993+
else if (speed == 100)
994+
val = bsp_priv->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV2 :
995+
RK3528_GMAC0_CLK_RMII_DIV2;
996+
else {
997+
dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
998+
return;
999+
}
1000+
1001+
reg = bsp_priv->id == 1 ? RK3528_VPU_GRF_GMAC_CON5 :
1002+
RK3528_VO_GRF_GMAC_CON;
1003+
1004+
regmap_write(bsp_priv->grf, reg, val);
1005+
}
1006+
1007+
static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv,
1008+
bool input, bool enable)
1009+
{
1010+
unsigned int val;
1011+
1012+
if (bsp_priv->id == 1) {
1013+
val = input ? RK3528_GMAC1_CLK_SELECT_IO :
1014+
RK3528_GMAC1_CLK_SELECT_CRU;
1015+
val |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE :
1016+
RK3528_GMAC1_CLK_RMII_GATE;
1017+
regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val);
1018+
} else {
1019+
val = enable ? RK3528_GMAC0_CLK_RMII_NOGATE :
1020+
RK3528_GMAC0_CLK_RMII_GATE;
1021+
regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, val);
1022+
}
1023+
}
1024+
1025+
static void rk3528_integrated_phy_powerup(struct rk_priv_data *bsp_priv)
1026+
{
1027+
rk_gmac_integrated_fephy_powerup(bsp_priv, RK3528_VO_GRF_MACPHY_CON0);
1028+
}
1029+
1030+
static void rk3528_integrated_phy_powerdown(struct rk_priv_data *bsp_priv)
1031+
{
1032+
rk_gmac_integrated_fephy_powerdown(bsp_priv, RK3528_VO_GRF_MACPHY_CON0);
1033+
}
1034+
1035+
static const struct rk_gmac_ops rk3528_ops = {
1036+
.set_to_rgmii = rk3528_set_to_rgmii,
1037+
.set_to_rmii = rk3528_set_to_rmii,
1038+
.set_rgmii_speed = rk3528_set_rgmii_speed,
1039+
.set_rmii_speed = rk3528_set_rmii_speed,
1040+
.set_clock_selection = rk3528_set_clock_selection,
1041+
.integrated_phy_powerup = rk3528_integrated_phy_powerup,
1042+
.integrated_phy_powerdown = rk3528_integrated_phy_powerdown,
1043+
.regs_valid = true,
1044+
.regs = {
1045+
0xffbd0000, /* gmac0 */
1046+
0xffbe0000, /* gmac1 */
1047+
0x0, /* sentinel */
1048+
},
1049+
};
1050+
8311051
#define RK3568_GRF_GMAC0_CON0 0x0380
8321052
#define RK3568_GRF_GMAC0_CON1 0x0384
8331053
#define RK3568_GRF_GMAC1_CON0 0x0388
@@ -1332,50 +1552,6 @@ static const struct rk_gmac_ops rv1126_ops = {
13321552
.set_rmii_speed = rv1126_set_rmii_speed,
13331553
};
13341554

1335-
#define RK_GRF_MACPHY_CON0 0xb00
1336-
#define RK_GRF_MACPHY_CON1 0xb04
1337-
#define RK_GRF_MACPHY_CON2 0xb08
1338-
#define RK_GRF_MACPHY_CON3 0xb0c
1339-
1340-
#define RK_MACPHY_ENABLE GRF_BIT(0)
1341-
#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
1342-
#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
1343-
#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
1344-
#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
1345-
#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
1346-
1347-
static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
1348-
{
1349-
if (priv->ops->integrated_phy_powerup)
1350-
priv->ops->integrated_phy_powerup(priv);
1351-
1352-
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
1353-
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
1354-
1355-
regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
1356-
regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
1357-
1358-
if (priv->phy_reset) {
1359-
/* PHY needs to be disabled before trying to reset it */
1360-
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1361-
if (priv->phy_reset)
1362-
reset_control_assert(priv->phy_reset);
1363-
usleep_range(10, 20);
1364-
if (priv->phy_reset)
1365-
reset_control_deassert(priv->phy_reset);
1366-
usleep_range(10, 20);
1367-
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
1368-
msleep(30);
1369-
}
1370-
}
1371-
1372-
static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
1373-
{
1374-
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1375-
if (priv->phy_reset)
1376-
reset_control_assert(priv->phy_reset);
1377-
}
1378-
13791555
static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
13801556
{
13811557
struct rk_priv_data *bsp_priv = plat->bsp_priv;
@@ -1671,16 +1847,16 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
16711847

16721848
pm_runtime_get_sync(dev);
16731849

1674-
if (bsp_priv->integrated_phy)
1675-
rk_gmac_integrated_phy_powerup(bsp_priv);
1850+
if (bsp_priv->integrated_phy && bsp_priv->ops->integrated_phy_powerup)
1851+
bsp_priv->ops->integrated_phy_powerup(bsp_priv);
16761852

16771853
return 0;
16781854
}
16791855

16801856
static void rk_gmac_powerdown(struct rk_priv_data *gmac)
16811857
{
1682-
if (gmac->integrated_phy)
1683-
rk_gmac_integrated_phy_powerdown(gmac);
1858+
if (gmac->integrated_phy && gmac->ops->integrated_phy_powerdown)
1859+
gmac->ops->integrated_phy_powerdown(gmac);
16841860

16851861
pm_runtime_put_sync(&gmac->pdev->dev);
16861862

@@ -1819,6 +1995,7 @@ static const struct of_device_id rk_gmac_dwmac_match[] = {
18191995
{ .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
18201996
{ .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
18211997
{ .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
1998+
{ .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops },
18221999
{ .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
18232000
{ .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops },
18242001
{ .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },

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