Skip to content

Commit 2904244

Browse files
mindachen1987ConchuOD
mindachen1987
authored and
ConchuOD
committed
riscv: dts: starfive: add PCIe dts configuration for JH7110
Add PCIe dts configuraion for JH7110 SoC platform. The Star64 only has one exposed PCIe port, so only the Mars and VisionFive 2 get two enabled. Signed-off-by: Minda Chen <[email protected]> Reviewed-by: Hal Feng <[email protected]> [conor: squash in star64's single exposed port] Signed-off-by: Conor Dooley <[email protected]>
1 parent 3f41368 commit 2904244

File tree

5 files changed

+167
-0
lines changed

5 files changed

+167
-0
lines changed

‎arch/riscv/boot/dts/starfive/jh7110-common.dtsi

Lines changed: 62 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -294,6 +294,20 @@
294294
status = "okay";
295295
};
296296

297+
&pcie0 {
298+
perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
299+
phys = <&pciephy0>;
300+
pinctrl-names = "default";
301+
pinctrl-0 = <&pcie0_pins>;
302+
};
303+
304+
&pcie1 {
305+
perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
306+
phys = <&pciephy1>;
307+
pinctrl-names = "default";
308+
pinctrl-0 = <&pcie1_pins>;
309+
};
310+
297311
&pwmdac {
298312
pinctrl-names = "default";
299313
pinctrl-0 = <&pwmdac_pins>;
@@ -473,6 +487,54 @@
473487
};
474488
};
475489

490+
pcie0_pins: pcie0-0 {
491+
clkreq-pins {
492+
pinmux = <GPIOMUX(27, GPOUT_LOW,
493+
GPOEN_DISABLE,
494+
GPI_NONE)>;
495+
bias-pull-down;
496+
drive-strength = <2>;
497+
input-enable;
498+
input-schmitt-disable;
499+
slew-rate = <0>;
500+
};
501+
502+
wake-pins {
503+
pinmux = <GPIOMUX(32, GPOUT_LOW,
504+
GPOEN_DISABLE,
505+
GPI_NONE)>;
506+
bias-pull-up;
507+
drive-strength = <2>;
508+
input-enable;
509+
input-schmitt-disable;
510+
slew-rate = <0>;
511+
};
512+
};
513+
514+
pcie1_pins: pcie1-0 {
515+
clkreq-pins {
516+
pinmux = <GPIOMUX(29, GPOUT_LOW,
517+
GPOEN_DISABLE,
518+
GPI_NONE)>;
519+
bias-pull-down;
520+
drive-strength = <2>;
521+
input-enable;
522+
input-schmitt-disable;
523+
slew-rate = <0>;
524+
};
525+
526+
wake-pins {
527+
pinmux = <GPIOMUX(21, GPOUT_LOW,
528+
GPOEN_DISABLE,
529+
GPI_NONE)>;
530+
bias-pull-up;
531+
drive-strength = <2>;
532+
input-enable;
533+
input-schmitt-disable;
534+
slew-rate = <0>;
535+
};
536+
};
537+
476538
pwmdac_pins: pwmdac-0 {
477539
pwmdac-pins {
478540
pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,

‎arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,13 @@
1717
assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
1818
};
1919

20+
&pcie0 {
21+
status = "okay";
22+
};
23+
24+
&pcie1 {
25+
status = "okay";
26+
};
2027

2128
&phy0 {
2229
motorcomm,tx-clk-adj-enabled;

‎arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,10 @@
3939
};
4040
};
4141

42+
&pcie1 {
43+
status = "okay";
44+
};
45+
4246
&phy0 {
4347
rx-internal-delay-ps = <1900>;
4448
tx-internal-delay-ps = <1500>;

‎arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,3 +32,11 @@
3232
&mmc0 {
3333
non-removable;
3434
};
35+
36+
&pcie0 {
37+
status = "okay";
38+
};
39+
40+
&pcie1 {
41+
status = "okay";
42+
};

‎arch/riscv/boot/dts/starfive/jh7110.dtsi

Lines changed: 86 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1214,5 +1214,91 @@
12141214
#reset-cells = <1>;
12151215
power-domains = <&pwrc JH7110_PD_VOUT>;
12161216
};
1217+
1218+
pcie0: pcie@940000000 {
1219+
compatible = "starfive,jh7110-pcie";
1220+
reg = <0x9 0x40000000 0x0 0x1000000>,
1221+
<0x0 0x2b000000 0x0 0x100000>;
1222+
reg-names = "cfg", "apb";
1223+
linux,pci-domain = <0>;
1224+
#address-cells = <3>;
1225+
#size-cells = <2>;
1226+
#interrupt-cells = <1>;
1227+
ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
1228+
<0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
1229+
interrupts = <56>;
1230+
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1231+
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
1232+
<0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
1233+
<0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
1234+
<0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
1235+
msi-controller;
1236+
device_type = "pci";
1237+
starfive,stg-syscon = <&stg_syscon>;
1238+
bus-range = <0x0 0xff>;
1239+
clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
1240+
<&stgcrg JH7110_STGCLK_PCIE0_TL>,
1241+
<&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,
1242+
<&stgcrg JH7110_STGCLK_PCIE0_APB>;
1243+
clock-names = "noc", "tl", "axi_mst0", "apb";
1244+
resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>,
1245+
<&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>,
1246+
<&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>,
1247+
<&stgcrg JH7110_STGRST_PCIE0_BRG>,
1248+
<&stgcrg JH7110_STGRST_PCIE0_CORE>,
1249+
<&stgcrg JH7110_STGRST_PCIE0_APB>;
1250+
reset-names = "mst0", "slv0", "slv", "brg",
1251+
"core", "apb";
1252+
status = "disabled";
1253+
1254+
pcie_intc0: interrupt-controller {
1255+
#address-cells = <0>;
1256+
#interrupt-cells = <1>;
1257+
interrupt-controller;
1258+
};
1259+
};
1260+
1261+
pcie1: pcie@9c0000000 {
1262+
compatible = "starfive,jh7110-pcie";
1263+
reg = <0x9 0xc0000000 0x0 0x1000000>,
1264+
<0x0 0x2c000000 0x0 0x100000>;
1265+
reg-names = "cfg", "apb";
1266+
linux,pci-domain = <1>;
1267+
#address-cells = <3>;
1268+
#size-cells = <2>;
1269+
#interrupt-cells = <1>;
1270+
ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
1271+
<0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
1272+
interrupts = <57>;
1273+
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1274+
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>,
1275+
<0x0 0x0 0x0 0x2 &pcie_intc1 0x2>,
1276+
<0x0 0x0 0x0 0x3 &pcie_intc1 0x3>,
1277+
<0x0 0x0 0x0 0x4 &pcie_intc1 0x4>;
1278+
msi-controller;
1279+
device_type = "pci";
1280+
starfive,stg-syscon = <&stg_syscon>;
1281+
bus-range = <0x0 0xff>;
1282+
clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
1283+
<&stgcrg JH7110_STGCLK_PCIE1_TL>,
1284+
<&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>,
1285+
<&stgcrg JH7110_STGCLK_PCIE1_APB>;
1286+
clock-names = "noc", "tl", "axi_mst0", "apb";
1287+
resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>,
1288+
<&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>,
1289+
<&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>,
1290+
<&stgcrg JH7110_STGRST_PCIE1_BRG>,
1291+
<&stgcrg JH7110_STGRST_PCIE1_CORE>,
1292+
<&stgcrg JH7110_STGRST_PCIE1_APB>;
1293+
reset-names = "mst0", "slv0", "slv", "brg",
1294+
"core", "apb";
1295+
status = "disabled";
1296+
1297+
pcie_intc1: interrupt-controller {
1298+
#address-cells = <0>;
1299+
#interrupt-cells = <1>;
1300+
interrupt-controller;
1301+
};
1302+
};
12171303
};
12181304
};

0 commit comments

Comments
 (0)