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arm64: dts: ti: Introduce AM62P5 family of SoCs
The AM62Px is an extension of the existing Sitara AM62x low-cost family of application processors built for Automotive and Linux Application development. Scalable Arm Cortex-A53 performance and embedded features, such as: multi high-definition display support, 3D-graphics acceleration, 4K video acceleration, and extensive peripherals make the AM62Px well-suited for a broad range of automation and industrial application, including automotive digital instrumentation, automotive displays, industrial HMI, and more. Some highlights of AM62P SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single core variants are provided in the same package to allow HW compatible designs. * One Device manager Cortext-R5F for system power and resource management, and one Cortex-R5F for Functional Safety or general-purpose usage. * One 3D GPU up to 50 GLFOPS * H.264/H.265 Video Encode/Decode. * Display support: 3x display support over OLDI/LVDS (1x OLDI-DL, 1x or 2x OLDI-SL), DSI, or DPI. Up to 3840x1080@60fps resolution * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3xMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, 1xCSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized Hardware Security Module with support for secure boot, debug security and crypto acceleration and trusted execution environment. * One 32-bit DDR Subsystem that supports LPDDR4, DDR4 memory types. * Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, enabling battery powered system design. For those interested, more details about this SoC can be found in the Technical Reference Manual here: https://www.ti.com/lit/pdf/spruj83 Signed-off-by: Bryan Brattlof <[email protected]> Acked-by: Andrew Davis <[email protected]> Reviewed-by: Dhruva Gole <[email protected]> Signed-off-by: Vignesh Raghavendra <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Nishanth Menon <[email protected]>
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‎arch/arm64/boot/dts/ti/k3-am62p-main.dtsi

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree file for the AM62P main domain peripherals
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* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_main {
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oc_sram: sram@70000000 {
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compatible = "mmio-sram";
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reg = <0x00 0x70000000 0x00 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00 0x00 0x70000000 0x10000>;
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};
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gic500: interrupt-controller@1800000 {
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
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<0x00 0x01880000 0x00 0xc0000>, /* GICR */
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<0x01 0x00000000 0x00 0x2000>, /* GICC */
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<0x01 0x00010000 0x00 0x1000>, /* GICH */
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<0x01 0x00020000 0x00 0x2000>; /* GICV */
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/*
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* vcpumntirq:
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* virtual CPU interface maintenance interrupt
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*/
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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gic_its: msi-controller@1820000 {
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compatible = "arm,gic-v3-its";
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reg = <0x00 0x01820000 0x00 0x10000>;
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socionext,synquacer-pre-its = <0x1000000 0x400000>;
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msi-controller;
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#msi-cells = <1>;
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};
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};
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dmss: bus@48000000 {
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bootph-all;
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compatible = "simple-mfd";
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#address-cells = <2>;
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#size-cells = <2>;
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dma-ranges;
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ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
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ti,sci-dev-id = <25>;
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secure_proxy_main: mailbox@4d000000 {
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bootph-all;
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compatible = "ti,am654-secure-proxy";
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#mbox-cells = <1>;
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reg-names = "target_data", "rt", "scfg";
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reg = <0x00 0x4d000000 0x00 0x80000>,
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<0x00 0x4a600000 0x00 0x80000>,
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<0x00 0x4a400000 0x00 0x80000>;
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interrupt-names = "rx_012";
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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dmsc: system-controller@44043000 {
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bootph-all;
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compatible = "ti,k2g-sci";
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ti,host-id = <12>;
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mbox-names = "rx", "tx";
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mboxes = <&secure_proxy_main 12>,
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<&secure_proxy_main 13>;
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reg-names = "debug_messages";
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reg = <0x00 0x44043000 0x00 0xfe0>;
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k3_pds: power-controller {
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bootph-all;
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compatible = "ti,sci-pm-domain";
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#power-domain-cells = <2>;
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};
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k3_clks: clock-controller {
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bootph-all;
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compatible = "ti,k2g-sci-clk";
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#clock-cells = <2>;
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};
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k3_reset: reset-controller {
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bootph-all;
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compatible = "ti,sci-reset";
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#reset-cells = <2>;
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};
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};
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main_pmx0: pinctrl@f4000 {
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bootph-all;
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compatible = "pinctrl-single";
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reg = <0x00 0xf4000 0x00 0x2ac>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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main_timer0: timer@2400000 {
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bootph-all;
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compatible = "ti,am654-timer";
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reg = <0x00 0x2400000 0x00 0x400>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 36 2>;
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clock-names = "fck";
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assigned-clocks = <&k3_clks 36 2>;
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assigned-clock-parents = <&k3_clks 36 3>;
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power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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};
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main_uart0: serial@2800000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02800000 0x00 0x100>;
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interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 146 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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main_uart1: serial@2810000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02810000 0x00 0x100>;
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interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 152 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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};

‎arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree file for the AM62P MCU domain peripherals
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* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_mcu {
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mcu_pmx0: pinctrl@4084000 {
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compatible = "pinctrl-single";
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reg = <0x00 0x04084000 0x00 0x88>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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};

‎arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree file for the AM62P wakeup domain peripherals
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* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_wakeup {
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wkup_conf: bus@43000000 {
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bootph-all;
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compatible = "simple-bus";
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reg = <0x00 0x43000000 0x00 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00 0x00 0x43000000 0x20000>;
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chipid: chipid@14 {
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bootph-all;
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compatible = "ti,am654-chipid";
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reg = <0x14 0x4>;
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};
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};
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wkup_uart0: serial@2b300000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x2b300000 0x00 0x100>;
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 114 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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};

‎arch/arm64/boot/dts/ti/k3-am62p.dtsi

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM62P SoC Family
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*
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* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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#include "k3-pinctrl.h"
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/ {
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model = "Texas Instruments K3 AM62P5 SoC";
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compatible = "ti,am62p5";
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interrupt-parent = <&gic500>;
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#address-cells = <2>;
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#size-cells = <2>;
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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psci: psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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};
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a53_timer0: timer-cl0-cpu0 {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
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};
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pmu: pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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cbass_main: bus@f0000 {
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bootph-all;
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
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<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
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<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
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<0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
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<0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
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<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
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<0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
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<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
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<0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
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<0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
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<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
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<0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
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<0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
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<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
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<0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
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<0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
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<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
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<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
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<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
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<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
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<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
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<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
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<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
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<0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
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<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
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<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
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/* MCU Domain Range */
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<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
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<0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>,
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<0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>,
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<0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>,
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<0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>,
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/* Wakeup Domain Range */
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<0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>,
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<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
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<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
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<0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>,
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<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>;
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cbass_mcu: bus@4000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */
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<0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
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<0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
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<0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */
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<0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */
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};
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cbass_wakeup: bus@b00000 {
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bootph-all;
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
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<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
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<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */
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<0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
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<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
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};
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};
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};
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/* Now include peripherals for each bus segment */
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#include "k3-am62p-main.dtsi"
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#include "k3-am62p-mcu.dtsi"
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#include "k3-am62p-wakeup.dtsi"

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