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andredkrzk
andred
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clk: samsung: gs101: add support for cmu_peric1
CMU_PERIC1 is the clock management unit used for the peric1 block which is used for additional USI, I3C and PWM interfaces/busses. Add support for muxes, dividers and gates of cmu_peric1, except for CLK_GOUT_PERIC1_IP which isn't well described in the datasheet and which downstream also ignores (similar to cmu_peric0). Two clocks have been marked as CLK_IS_CRITICAL for the following reason: * disabling them makes it impossible to access any peric1 registers, (including those two registers). * disabling gout_peric1_lhm_axi_p_peric1_i_clk sometimes has the additional effect of making the whole system unresponsive. One clock marked as CLK_IGNORE_UNUSED needs to be kept on until we have updated the respective driver for the following reason: * gout_peric1_gpio_peric1_pclk is required by the pinctrl configuration. With this clock disabled, reconfiguring the pins (for USI/I2C, USI/UART) will hang during register access. Since pinctrl-samsung doesn't support a clock at the moment, we just keep the kernel from disabling it at boot, until we have an update for pinctrl-samsung, at which point we'll drop the flag. Signed-off-by: André Draszik <[email protected]> Reviewed-by: Sam Protsenko <[email protected]> Reviewed-by: Peter Griffin <[email protected]> Reviewed-by: Tudor Ambarus <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
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‎drivers/clk/samsung/clk-gs101.c

Lines changed: 346 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@
2121
#define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1)
2222
#define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
2323
#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
24+
#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)
2425

2526
/* ---- CMU_TOP ------------------------------------------------------------- */
2627

@@ -3066,6 +3067,348 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = {
30663067
.clk_name = "bus",
30673068
};
30683069

3070+
/* ---- CMU_PERIC1 ---------------------------------------------------------- */
3071+
3072+
/* Register Offset definitions for CMU_PERIC1 (0x10c00000) */
3073+
#define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600
3074+
#define PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER 0x0604
3075+
#define PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER 0x0610
3076+
#define PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER 0x0614
3077+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0620
3078+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0624
3079+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0630
3080+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0634
3081+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0640
3082+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0644
3083+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0650
3084+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0654
3085+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0660
3086+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0664
3087+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0670
3088+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0674
3089+
#define PERIC1_CMU_PERIC1_CONTROLLER_OPTION 0x0800
3090+
#define CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0 0x0810
3091+
#define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800
3092+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI 0x1804
3093+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808
3094+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c
3095+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810
3096+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814
3097+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI 0x1818
3098+
#define CLK_CON_BUF_CLKBUF_PERIC1_IP 0x2000
3099+
#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK 0x2004
3100+
#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK 0x2008
3101+
#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK 0x200c
3102+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK 0x2010
3103+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK 0x2014
3104+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK 0x2018
3105+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK 0x201c
3106+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 0x2020
3107+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 0x2024
3108+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 0x2028
3109+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x202c
3110+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 0x2030
3111+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 0x2034
3112+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 0x2038
3113+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x203c
3114+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15 0x2040
3115+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2044
3116+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2048
3117+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x204c
3118+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2050
3119+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2054
3120+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x2058
3121+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK 0x205c
3122+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK 0x2060
3123+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK 0x2064
3124+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK 0x2068
3125+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK 0x206c
3126+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK 0x2070
3127+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK 0x2074
3128+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK 0x2078
3129+
#define DMYQCH_CON_PERIC1_TOP0_QCH_S 0x3000
3130+
#define PCH_CON_LHM_AXI_P_PERIC1_PCH 0x3004
3131+
#define QCH_CON_D_TZPC_PERIC1_QCH 0x3008
3132+
#define QCH_CON_GPC_PERIC1_QCH 0x300c
3133+
#define QCH_CON_GPIO_PERIC1_QCH 0x3010
3134+
#define QCH_CON_LHM_AXI_P_PERIC1_QCH 0x3014
3135+
#define QCH_CON_PERIC1_CMU_PERIC1_QCH 0x3018
3136+
#define QCH_CON_PERIC1_TOP0_QCH_I3C0 0x301c
3137+
#define QCH_CON_PERIC1_TOP0_QCH_PWM 0x3020
3138+
#define QCH_CON_PERIC1_TOP0_QCH_USI0_USI 0x3024
3139+
#define QCH_CON_PERIC1_TOP0_QCH_USI10_USI 0x3028
3140+
#define QCH_CON_PERIC1_TOP0_QCH_USI11_USI 0x302c
3141+
#define QCH_CON_PERIC1_TOP0_QCH_USI12_USI 0x3030
3142+
#define QCH_CON_PERIC1_TOP0_QCH_USI13_USI 0x3034
3143+
#define QCH_CON_PERIC1_TOP0_QCH_USI9_USI 0x3038
3144+
#define QCH_CON_SYSREG_PERIC1_QCH 0x303c
3145+
#define QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1 0x3c00
3146+
3147+
static const unsigned long peric1_clk_regs[] __initconst = {
3148+
PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER,
3149+
PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER,
3150+
PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER,
3151+
PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER,
3152+
PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER,
3153+
PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER,
3154+
PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER,
3155+
PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER,
3156+
PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER,
3157+
PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER,
3158+
PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER,
3159+
PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER,
3160+
PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER,
3161+
PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER,
3162+
PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER,
3163+
PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER,
3164+
PERIC1_CMU_PERIC1_CONTROLLER_OPTION,
3165+
CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0,
3166+
CLK_CON_DIV_DIV_CLK_PERIC1_I3C,
3167+
CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI,
3168+
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
3169+
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
3170+
CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
3171+
CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,
3172+
CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI,
3173+
CLK_CON_BUF_CLKBUF_PERIC1_IP,
3174+
CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
3175+
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK,
3176+
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK,
3177+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,
3178+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK,
3179+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
3180+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
3181+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
3182+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
3183+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
3184+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
3185+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
3186+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
3187+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
3188+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
3189+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15,
3190+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
3191+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
3192+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
3193+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
3194+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
3195+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
3196+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
3197+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK,
3198+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK,
3199+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,
3200+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK,
3201+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK,
3202+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK,
3203+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
3204+
DMYQCH_CON_PERIC1_TOP0_QCH_S,
3205+
PCH_CON_LHM_AXI_P_PERIC1_PCH,
3206+
QCH_CON_D_TZPC_PERIC1_QCH,
3207+
QCH_CON_GPC_PERIC1_QCH,
3208+
QCH_CON_GPIO_PERIC1_QCH,
3209+
QCH_CON_LHM_AXI_P_PERIC1_QCH,
3210+
QCH_CON_PERIC1_CMU_PERIC1_QCH,
3211+
QCH_CON_PERIC1_TOP0_QCH_I3C0,
3212+
QCH_CON_PERIC1_TOP0_QCH_PWM,
3213+
QCH_CON_PERIC1_TOP0_QCH_USI0_USI,
3214+
QCH_CON_PERIC1_TOP0_QCH_USI10_USI,
3215+
QCH_CON_PERIC1_TOP0_QCH_USI11_USI,
3216+
QCH_CON_PERIC1_TOP0_QCH_USI12_USI,
3217+
QCH_CON_PERIC1_TOP0_QCH_USI13_USI,
3218+
QCH_CON_PERIC1_TOP0_QCH_USI9_USI,
3219+
QCH_CON_SYSREG_PERIC1_QCH,
3220+
QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1,
3221+
};
3222+
3223+
/* List of parent clocks for Muxes in CMU_PERIC1 */
3224+
PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_cmu_peric1_bus" };
3225+
PNAME(mout_peric1_nonbususer_p) = { "oscclk", "dout_cmu_peric1_ip" };
3226+
3227+
static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
3228+
MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user",
3229+
mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1),
3230+
MUX(CLK_MOUT_PERIC1_I3C_USER,
3231+
"mout_peric1_i3c_user", mout_peric1_nonbususer_p,
3232+
PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 4, 1),
3233+
MUX(CLK_MOUT_PERIC1_USI0_USI_USER,
3234+
"mout_peric1_usi0_usi_user", mout_peric1_nonbususer_p,
3235+
PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4, 1),
3236+
MUX(CLK_MOUT_PERIC1_USI10_USI_USER,
3237+
"mout_peric1_usi10_usi_user", mout_peric1_nonbususer_p,
3238+
PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1),
3239+
MUX(CLK_MOUT_PERIC1_USI11_USI_USER,
3240+
"mout_peric1_usi11_usi_user", mout_peric1_nonbususer_p,
3241+
PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1),
3242+
MUX(CLK_MOUT_PERIC1_USI12_USI_USER,
3243+
"mout_peric1_usi12_usi_user", mout_peric1_nonbususer_p,
3244+
PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1),
3245+
MUX(CLK_MOUT_PERIC1_USI13_USI_USER,
3246+
"mout_peric1_usi13_usi_user", mout_peric1_nonbususer_p,
3247+
PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4, 1),
3248+
MUX(CLK_MOUT_PERIC1_USI9_USI_USER,
3249+
"mout_peric1_usi9_usi_user", mout_peric1_nonbususer_p,
3250+
PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4, 1),
3251+
};
3252+
3253+
static const struct samsung_div_clock peric1_div_clks[] __initconst = {
3254+
DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c", "mout_peric1_i3c_user",
3255+
CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4),
3256+
DIV(CLK_DOUT_PERIC1_USI0_USI,
3257+
"dout_peric1_usi0_usi", "mout_peric1_usi0_usi_user",
3258+
CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0, 4),
3259+
DIV(CLK_DOUT_PERIC1_USI10_USI,
3260+
"dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user",
3261+
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4),
3262+
DIV(CLK_DOUT_PERIC1_USI11_USI,
3263+
"dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user",
3264+
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4),
3265+
DIV(CLK_DOUT_PERIC1_USI12_USI,
3266+
"dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user",
3267+
CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4),
3268+
DIV(CLK_DOUT_PERIC1_USI13_USI,
3269+
"dout_peric1_usi13_usi", "mout_peric1_usi13_usi_user",
3270+
CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0, 4),
3271+
DIV(CLK_DOUT_PERIC1_USI9_USI,
3272+
"dout_peric1_usi9_usi", "mout_peric1_usi9_usi_user",
3273+
CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0, 4),
3274+
};
3275+
3276+
static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
3277+
GATE(CLK_GOUT_PERIC1_PCLK,
3278+
"gout_peric1_peric1_pclk", "mout_peric1_bus_user",
3279+
CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
3280+
21, CLK_IS_CRITICAL, 0),
3281+
GATE(CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK,
3282+
"gout_peric1_clk_peric1_i3c_clk", "dout_peric1_i3c",
3283+
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK,
3284+
21, 0, 0),
3285+
GATE(CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK,
3286+
"gout_peric1_clk_peric1_oscclk_clk", "oscclk",
3287+
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK,
3288+
21, 0, 0),
3289+
GATE(CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK,
3290+
"gout_peric1_d_tzpc_peric1_pclk", "mout_peric1_bus_user",
3291+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,
3292+
21, 0, 0),
3293+
GATE(CLK_GOUT_PERIC1_GPC_PERIC1_PCLK,
3294+
"gout_peric1_gpc_peric1_pclk", "mout_peric1_bus_user",
3295+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK,
3296+
21, 0, 0),
3297+
GATE(CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK,
3298+
"gout_peric1_gpio_peric1_pclk", "mout_peric1_bus_user",
3299+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
3300+
21, CLK_IGNORE_UNUSED, 0),
3301+
GATE(CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK,
3302+
"gout_peric1_lhm_axi_p_peric1_i_clk", "mout_peric1_bus_user",
3303+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
3304+
21, CLK_IS_CRITICAL, 0),
3305+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1,
3306+
"gout_peric1_peric1_top0_ipclk_1", "dout_peric1_usi0_usi",
3307+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
3308+
21, 0, 0),
3309+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2,
3310+
"gout_peric1_peric1_top0_ipclk_2", "dout_peric1_usi9_usi",
3311+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
3312+
21, 0, 0),
3313+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3,
3314+
"gout_peric1_peric1_top0_ipclk_3", "dout_peric1_usi10_usi",
3315+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
3316+
21, 0, 0),
3317+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4,
3318+
"gout_peric1_peric1_top0_ipclk_4", "dout_peric1_usi11_usi",
3319+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
3320+
21, 0, 0),
3321+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5,
3322+
"gout_peric1_peric1_top0_ipclk_5", "dout_peric1_usi12_usi",
3323+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
3324+
21, 0, 0),
3325+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6,
3326+
"gout_peric1_peric1_top0_ipclk_6", "dout_peric1_usi13_usi",
3327+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
3328+
21, 0, 0),
3329+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8,
3330+
"gout_peric1_peric1_top0_ipclk_8", "dout_peric1_i3c",
3331+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
3332+
21, 0, 0),
3333+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1,
3334+
"gout_peric1_peric1_top0_pclk_1", "mout_peric1_bus_user",
3335+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
3336+
21, 0, 0),
3337+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15,
3338+
"gout_peric1_peric1_top0_pclk_15", "mout_peric1_bus_user",
3339+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15,
3340+
21, 0, 0),
3341+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2,
3342+
"gout_peric1_peric1_top0_pclk_2", "mout_peric1_bus_user",
3343+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
3344+
21, 0, 0),
3345+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3,
3346+
"gout_peric1_peric1_top0_pclk_3", "mout_peric1_bus_user",
3347+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
3348+
21, 0, 0),
3349+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4,
3350+
"gout_peric1_peric1_top0_pclk_4", "mout_peric1_bus_user",
3351+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
3352+
21, 0, 0),
3353+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5,
3354+
"gout_peric1_peric1_top0_pclk_5", "mout_peric1_bus_user",
3355+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
3356+
21, 0, 0),
3357+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6,
3358+
"gout_peric1_peric1_top0_pclk_6", "mout_peric1_bus_user",
3359+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
3360+
21, 0, 0),
3361+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8,
3362+
"gout_peric1_peric1_top0_pclk_8", "mout_peric1_bus_user",
3363+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
3364+
21, 0, 0),
3365+
GATE(CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK,
3366+
"gout_peric1_clk_peric1_busp_clk", "mout_peric1_bus_user",
3367+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
3368+
21, 0, 0),
3369+
GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK,
3370+
"gout_peric1_clk_peric1_usi0_usi_clk", "dout_peric1_usi0_usi",
3371+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK,
3372+
21, 0, 0),
3373+
GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK,
3374+
"gout_peric1_clk_peric1_usi10_usi_clk", "dout_peric1_usi10_usi",
3375+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK,
3376+
21, 0, 0),
3377+
GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK,
3378+
"gout_peric1_clk_peric1_usi11_usi_clk", "dout_peric1_usi11_usi",
3379+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,
3380+
21, 0, 0),
3381+
GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK,
3382+
"gout_peric1_clk_peric1_usi12_usi_clk", "dout_peric1_usi12_usi",
3383+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK,
3384+
21, 0, 0),
3385+
GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK,
3386+
"gout_peric1_clk_peric1_usi13_usi_clk", "dout_peric1_usi13_usi",
3387+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK,
3388+
21, 0, 0),
3389+
GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK,
3390+
"gout_peric1_clk_peric1_usi9_usi_clk", "dout_peric1_usi9_usi",
3391+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK,
3392+
21, 0, 0),
3393+
GATE(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK,
3394+
"gout_peric1_sysreg_peric1_pclk", "mout_peric1_bus_user",
3395+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
3396+
21, 0, 0),
3397+
};
3398+
3399+
static const struct samsung_cmu_info peric1_cmu_info __initconst = {
3400+
.mux_clks = peric1_mux_clks,
3401+
.nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
3402+
.div_clks = peric1_div_clks,
3403+
.nr_div_clks = ARRAY_SIZE(peric1_div_clks),
3404+
.gate_clks = peric1_gate_clks,
3405+
.nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
3406+
.nr_clk_ids = CLKS_NR_PERIC1,
3407+
.clk_regs = peric1_clk_regs,
3408+
.nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
3409+
.clk_name = "bus",
3410+
};
3411+
30693412
/* ---- platform_driver ----------------------------------------------------- */
30703413

30713414
static int __init gs101_cmu_probe(struct platform_device *pdev)
@@ -3086,6 +3429,9 @@ static const struct of_device_id gs101_cmu_of_match[] = {
30863429
}, {
30873430
.compatible = "google,gs101-cmu-peric0",
30883431
.data = &peric0_cmu_info,
3432+
}, {
3433+
.compatible = "google,gs101-cmu-peric1",
3434+
.data = &peric1_cmu_info,
30893435
}, {
30903436
},
30913437
};

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