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Qi Taoherbertx
Qi Tao
authored and
herbertx
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crypto: hisilicon - support querying the capability register
Query the capability register status of accelerator devices (SEC, HPRE and ZIP) through the debugfs interface, for example: cat cap_regs. The purpose is to improve the robustness and locability of hardware devices and drivers. Signed-off-by: Qi Tao <[email protected]> Signed-off-by: Chenghai Huang <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
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‎Documentation/ABI/testing/debugfs-hisi-hpre

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -184,3 +184,10 @@ Date: Apr 2020
184184
Contact: [email protected]
185185
Description: Dump the total number of time out requests.
186186
Available for both PF and VF, and take no other effect on HPRE.
187+
188+
What: /sys/kernel/debug/hisi_hpre/<bdf>/cap_regs
189+
Date: Oct 2024
190+
Contact: [email protected]
191+
Description: Dump the values of the qm and hpre capability bit registers and
192+
support the query of device specifications to facilitate fault locating.
193+
Available for both PF and VF, and take no other effect on HPRE.

‎Documentation/ABI/testing/debugfs-hisi-sec

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -157,3 +157,10 @@ Contact: [email protected]
157157
Description: Dump the total number of completed but marked error requests
158158
to be received.
159159
Available for both PF and VF, and take no other effect on SEC.
160+
161+
What: /sys/kernel/debug/hisi_sec2/<bdf>/cap_regs
162+
Date: Oct 2024
163+
Contact: [email protected]
164+
Description: Dump the values of the qm and sec capability bit registers and
165+
support the query of device specifications to facilitate fault locating.
166+
Available for both PF and VF, and take no other effect on SEC.

‎Documentation/ABI/testing/debugfs-hisi-zip

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -158,3 +158,10 @@ Contact: [email protected]
158158
Description: Dump the total number of BD type error requests
159159
to be received.
160160
Available for both PF and VF, and take no other effect on ZIP.
161+
162+
What: /sys/kernel/debug/hisi_zip/<bdf>/cap_regs
163+
Date: Oct 2024
164+
Contact: [email protected]
165+
Description: Dump the values of the qm and zip capability bit registers and
166+
support the query of device specifications to facilitate fault locating.
167+
Available for both PF and VF, and take no other effect on ZIP.

‎drivers/crypto/hisilicon/hpre/hpre.h

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -100,6 +100,29 @@ struct hpre_sqe {
100100
__le32 rsvd1[_HPRE_SQE_ALIGN_EXT];
101101
};
102102

103+
enum hpre_cap_table_type {
104+
QM_RAS_NFE_TYPE = 0x0,
105+
QM_RAS_NFE_RESET,
106+
QM_RAS_CE_TYPE,
107+
HPRE_RAS_NFE_TYPE,
108+
HPRE_RAS_NFE_RESET,
109+
HPRE_RAS_CE_TYPE,
110+
HPRE_CORE_INFO,
111+
HPRE_CORE_EN,
112+
HPRE_DRV_ALG_BITMAP,
113+
HPRE_ALG_BITMAP,
114+
HPRE_CORE1_BITMAP_CAP,
115+
HPRE_CORE2_BITMAP_CAP,
116+
HPRE_CORE3_BITMAP_CAP,
117+
HPRE_CORE4_BITMAP_CAP,
118+
HPRE_CORE5_BITMAP_CAP,
119+
HPRE_CORE6_BITMAP_CAP,
120+
HPRE_CORE7_BITMAP_CAP,
121+
HPRE_CORE8_BITMAP_CAP,
122+
HPRE_CORE9_BITMAP_CAP,
123+
HPRE_CORE10_BITMAP_CAP,
124+
};
125+
103126
struct hisi_qp *hpre_create_qp(u8 type);
104127
int hpre_algs_register(struct hisi_qm *qm);
105128
void hpre_algs_unregister(struct hisi_qm *qm);

‎drivers/crypto/hisilicon/hpre/hpre_main.c

Lines changed: 91 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
#include <linux/uacce.h>
1414
#include "hpre.h"
1515

16+
#define CAP_FILE_PERMISSION 0444
1617
#define HPRE_CTRL_CNT_CLR_CE_BIT BIT(0)
1718
#define HPRE_CTRL_CNT_CLR_CE 0x301000
1819
#define HPRE_FSM_MAX_CNT 0x301008
@@ -203,7 +204,7 @@ static const struct hisi_qm_cap_info hpre_basic_info[] = {
203204
{HPRE_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0xBFFC3E},
204205
{HPRE_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x22, 0xBFFC3E},
205206
{HPRE_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1},
206-
{HPRE_CLUSTER_NUM_CAP, 0x313c, 20, GENMASK(3, 0), 0x0, 0x4, 0x1},
207+
{HPRE_CLUSTER_NUM_CAP, 0x313c, 20, GENMASK(3, 0), 0x0, 0x4, 0x1},
207208
{HPRE_CORE_TYPE_NUM_CAP, 0x313c, 16, GENMASK(3, 0), 0x0, 0x2, 0x2},
208209
{HPRE_CORE_NUM_CAP, 0x313c, 8, GENMASK(7, 0), 0x0, 0x8, 0xA},
209210
{HPRE_CLUSTER_CORE_NUM_CAP, 0x313c, 0, GENMASK(7, 0), 0x0, 0x2, 0xA},
@@ -222,18 +223,27 @@ static const struct hisi_qm_cap_info hpre_basic_info[] = {
222223
{HPRE_CORE10_ALG_BITMAP_CAP, 0x3170, 0, GENMASK(31, 0), 0x0, 0x10, 0x10}
223224
};
224225

225-
enum hpre_pre_store_cap_idx {
226-
HPRE_CLUSTER_NUM_CAP_IDX = 0x0,
227-
HPRE_CORE_ENABLE_BITMAP_CAP_IDX,
228-
HPRE_DRV_ALG_BITMAP_CAP_IDX,
229-
HPRE_DEV_ALG_BITMAP_CAP_IDX,
230-
};
231-
232-
static const u32 hpre_pre_store_caps[] = {
233-
HPRE_CLUSTER_NUM_CAP,
234-
HPRE_CORE_ENABLE_BITMAP_CAP,
235-
HPRE_DRV_ALG_BITMAP_CAP,
236-
HPRE_DEV_ALG_BITMAP_CAP,
226+
static const struct hisi_qm_cap_query_info hpre_cap_query_info[] = {
227+
{QM_RAS_NFE_TYPE, "QM_RAS_NFE_TYPE ", 0x3124, 0x0, 0x1C37, 0x7C37},
228+
{QM_RAS_NFE_RESET, "QM_RAS_NFE_RESET ", 0x3128, 0x0, 0xC77, 0x6C77},
229+
{QM_RAS_CE_TYPE, "QM_RAS_CE_TYPE ", 0x312C, 0x0, 0x8, 0x8},
230+
{HPRE_RAS_NFE_TYPE, "HPRE_RAS_NFE_TYPE ", 0x3130, 0x0, 0x3FFFFE, 0x1FFFC3E},
231+
{HPRE_RAS_NFE_RESET, "HPRE_RAS_NFE_RESET ", 0x3134, 0x0, 0x3FFFFE, 0xBFFC3E},
232+
{HPRE_RAS_CE_TYPE, "HPRE_RAS_CE_TYPE ", 0x3138, 0x0, 0x1, 0x1},
233+
{HPRE_CORE_INFO, "HPRE_CORE_INFO ", 0x313c, 0x0, 0x420802, 0x120A0A},
234+
{HPRE_CORE_EN, "HPRE_CORE_EN ", 0x3140, 0x0, 0xF, 0x3FF},
235+
{HPRE_DRV_ALG_BITMAP, "HPRE_DRV_ALG_BITMAP ", 0x3144, 0x0, 0x03, 0x27},
236+
{HPRE_ALG_BITMAP, "HPRE_ALG_BITMAP ", 0x3148, 0x0, 0x03, 0x7F},
237+
{HPRE_CORE1_BITMAP_CAP, "HPRE_CORE1_BITMAP_CAP ", 0x314c, 0x0, 0x7F, 0x7F},
238+
{HPRE_CORE2_BITMAP_CAP, "HPRE_CORE2_BITMAP_CAP ", 0x3150, 0x0, 0x7F, 0x7F},
239+
{HPRE_CORE3_BITMAP_CAP, "HPRE_CORE3_BITMAP_CAP ", 0x3154, 0x0, 0x7F, 0x7F},
240+
{HPRE_CORE4_BITMAP_CAP, "HPRE_CORE4_BITMAP_CAP ", 0x3158, 0x0, 0x7F, 0x7F},
241+
{HPRE_CORE5_BITMAP_CAP, "HPRE_CORE5_BITMAP_CAP ", 0x315c, 0x0, 0x7F, 0x7F},
242+
{HPRE_CORE6_BITMAP_CAP, "HPRE_CORE6_BITMAP_CAP ", 0x3160, 0x0, 0x7F, 0x7F},
243+
{HPRE_CORE7_BITMAP_CAP, "HPRE_CORE7_BITMAP_CAP ", 0x3164, 0x0, 0x7F, 0x7F},
244+
{HPRE_CORE8_BITMAP_CAP, "HPRE_CORE8_BITMAP_CAP ", 0x3168, 0x0, 0x7F, 0x7F},
245+
{HPRE_CORE9_BITMAP_CAP, "HPRE_CORE9_BITMAP_CAP ", 0x316c, 0x0, 0x10, 0x10},
246+
{HPRE_CORE10_BITMAP_CAP, "HPRE_CORE10_BITMAP_CAP ", 0x3170, 0x0, 0x10, 0x10},
237247
};
238248

239249
static const struct hpre_hw_error hpre_hw_errors[] = {
@@ -360,7 +370,7 @@ bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg)
360370
{
361371
u32 cap_val;
362372

363-
cap_val = qm->cap_tables.dev_cap_table[HPRE_DRV_ALG_BITMAP_CAP_IDX].cap_val;
373+
cap_val = qm->cap_tables.dev_cap_table[HPRE_DRV_ALG_BITMAP].cap_val;
364374
if (alg & cap_val)
365375
return true;
366376

@@ -503,14 +513,17 @@ static int hpre_cfg_by_dsm(struct hisi_qm *qm)
503513
static int hpre_set_cluster(struct hisi_qm *qm)
504514
{
505515
struct device *dev = &qm->pdev->dev;
506-
unsigned long offset;
507516
u32 cluster_core_mask;
517+
unsigned long offset;
518+
u32 hpre_core_info;
508519
u8 clusters_num;
509520
u32 val = 0;
510521
int ret, i;
511522

512-
cluster_core_mask = qm->cap_tables.dev_cap_table[HPRE_CORE_ENABLE_BITMAP_CAP_IDX].cap_val;
513-
clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
523+
cluster_core_mask = qm->cap_tables.dev_cap_table[HPRE_CORE_EN].cap_val;
524+
hpre_core_info = qm->cap_tables.dev_cap_table[HPRE_CORE_INFO].cap_val;
525+
clusters_num = (hpre_core_info >> hpre_basic_info[HPRE_CLUSTER_NUM_CAP].shift) &
526+
hpre_basic_info[HPRE_CLUSTER_NUM_CAP].mask;
514527
for (i = 0; i < clusters_num; i++) {
515528
offset = i * HPRE_CLSTR_ADDR_INTRVL;
516529

@@ -595,6 +608,7 @@ static void hpre_enable_clock_gate(struct hisi_qm *qm)
595608
{
596609
unsigned long offset;
597610
u8 clusters_num, i;
611+
u32 hpre_core_info;
598612
u32 val;
599613

600614
if (qm->ver < QM_HW_V3)
@@ -608,7 +622,9 @@ static void hpre_enable_clock_gate(struct hisi_qm *qm)
608622
val |= HPRE_PEH_CFG_AUTO_GATE_EN;
609623
writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE);
610624

611-
clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
625+
hpre_core_info = qm->cap_tables.dev_cap_table[HPRE_CORE_INFO].cap_val;
626+
clusters_num = (hpre_core_info >> hpre_basic_info[HPRE_CLUSTER_NUM_CAP].shift) &
627+
hpre_basic_info[HPRE_CLUSTER_NUM_CAP].mask;
612628
for (i = 0; i < clusters_num; i++) {
613629
offset = (unsigned long)i * HPRE_CLSTR_ADDR_INTRVL;
614630
val = readl(qm->io_base + offset + HPRE_CLUSTER_DYN_CTL);
@@ -625,6 +641,7 @@ static void hpre_disable_clock_gate(struct hisi_qm *qm)
625641
{
626642
unsigned long offset;
627643
u8 clusters_num, i;
644+
u32 hpre_core_info;
628645
u32 val;
629646

630647
if (qm->ver < QM_HW_V3)
@@ -638,7 +655,9 @@ static void hpre_disable_clock_gate(struct hisi_qm *qm)
638655
val &= ~HPRE_PEH_CFG_AUTO_GATE_EN;
639656
writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE);
640657

641-
clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
658+
hpre_core_info = qm->cap_tables.dev_cap_table[HPRE_CORE_INFO].cap_val;
659+
clusters_num = (hpre_core_info >> hpre_basic_info[HPRE_CLUSTER_NUM_CAP].shift) &
660+
hpre_basic_info[HPRE_CLUSTER_NUM_CAP].mask;
642661
for (i = 0; i < clusters_num; i++) {
643662
offset = (unsigned long)i * HPRE_CLSTR_ADDR_INTRVL;
644663
val = readl(qm->io_base + offset + HPRE_CLUSTER_DYN_CTL);
@@ -711,11 +730,14 @@ static int hpre_set_user_domain_and_cache(struct hisi_qm *qm)
711730
static void hpre_cnt_regs_clear(struct hisi_qm *qm)
712731
{
713732
unsigned long offset;
733+
u32 hpre_core_info;
714734
u8 clusters_num;
715735
int i;
716736

717737
/* clear clusterX/cluster_ctrl */
718-
clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
738+
hpre_core_info = qm->cap_tables.dev_cap_table[HPRE_CORE_INFO].cap_val;
739+
clusters_num = (hpre_core_info >> hpre_basic_info[HPRE_CLUSTER_NUM_CAP].shift) &
740+
hpre_basic_info[HPRE_CLUSTER_NUM_CAP].mask;
719741
for (i = 0; i < clusters_num; i++) {
720742
offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL;
721743
writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY);
@@ -1007,10 +1029,13 @@ static int hpre_cluster_debugfs_init(struct hisi_qm *qm)
10071029
char buf[HPRE_DBGFS_VAL_MAX_LEN];
10081030
struct debugfs_regset32 *regset;
10091031
struct dentry *tmp_d;
1032+
u32 hpre_core_info;
10101033
u8 clusters_num;
10111034
int i, ret;
10121035

1013-
clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
1036+
hpre_core_info = qm->cap_tables.dev_cap_table[HPRE_CORE_INFO].cap_val;
1037+
clusters_num = (hpre_core_info >> hpre_basic_info[HPRE_CLUSTER_NUM_CAP].shift) &
1038+
hpre_basic_info[HPRE_CLUSTER_NUM_CAP].mask;
10141039
for (i = 0; i < clusters_num; i++) {
10151040
ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i);
10161041
if (ret >= HPRE_DBGFS_VAL_MAX_LEN)
@@ -1053,6 +1078,26 @@ static int hpre_ctrl_debug_init(struct hisi_qm *qm)
10531078
return hpre_cluster_debugfs_init(qm);
10541079
}
10551080

1081+
static int hpre_cap_regs_show(struct seq_file *s, void *unused)
1082+
{
1083+
struct hisi_qm *qm = s->private;
1084+
u32 i, size;
1085+
1086+
size = qm->cap_tables.qm_cap_size;
1087+
for (i = 0; i < size; i++)
1088+
seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.qm_cap_table[i].name,
1089+
qm->cap_tables.qm_cap_table[i].cap_val);
1090+
1091+
size = qm->cap_tables.dev_cap_size;
1092+
for (i = 0; i < size; i++)
1093+
seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.dev_cap_table[i].name,
1094+
qm->cap_tables.dev_cap_table[i].cap_val);
1095+
1096+
return 0;
1097+
}
1098+
1099+
DEFINE_SHOW_ATTRIBUTE(hpre_cap_regs);
1100+
10561101
static void hpre_dfx_debug_init(struct hisi_qm *qm)
10571102
{
10581103
struct dfx_diff_registers *hpre_regs = qm->debug.acc_diff_regs;
@@ -1071,6 +1116,9 @@ static void hpre_dfx_debug_init(struct hisi_qm *qm)
10711116
if (qm->fun_type == QM_HW_PF && hpre_regs)
10721117
debugfs_create_file("diff_regs", 0444, parent,
10731118
qm, &hpre_diff_regs_fops);
1119+
1120+
debugfs_create_file("cap_regs", CAP_FILE_PERMISSION,
1121+
qm->debug.debug_root, qm, &hpre_cap_regs_fops);
10741122
}
10751123

10761124
static int hpre_debugfs_init(struct hisi_qm *qm)
@@ -1118,26 +1166,33 @@ static int hpre_pre_store_cap_reg(struct hisi_qm *qm)
11181166
{
11191167
struct hisi_qm_cap_record *hpre_cap;
11201168
struct device *dev = &qm->pdev->dev;
1169+
u32 hpre_core_info;
1170+
u8 clusters_num;
11211171
size_t i, size;
11221172

1123-
size = ARRAY_SIZE(hpre_pre_store_caps);
1173+
size = ARRAY_SIZE(hpre_cap_query_info);
11241174
hpre_cap = devm_kzalloc(dev, sizeof(*hpre_cap) * size, GFP_KERNEL);
11251175
if (!hpre_cap)
11261176
return -ENOMEM;
11271177

11281178
for (i = 0; i < size; i++) {
1129-
hpre_cap[i].type = hpre_pre_store_caps[i];
1130-
hpre_cap[i].cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info,
1131-
hpre_pre_store_caps[i], qm->cap_ver);
1179+
hpre_cap[i].type = hpre_cap_query_info[i].type;
1180+
hpre_cap[i].name = hpre_cap_query_info[i].name;
1181+
hpre_cap[i].cap_val = hisi_qm_get_cap_value(qm, hpre_cap_query_info,
1182+
i, qm->cap_ver);
11321183
}
11331184

1134-
if (hpre_cap[HPRE_CLUSTER_NUM_CAP_IDX].cap_val > HPRE_CLUSTERS_NUM_MAX) {
1185+
hpre_core_info = hpre_cap[HPRE_CORE_INFO].cap_val;
1186+
clusters_num = (hpre_core_info >> hpre_basic_info[HPRE_CLUSTER_NUM_CAP].shift) &
1187+
hpre_basic_info[HPRE_CLUSTER_NUM_CAP].mask;
1188+
if (clusters_num > HPRE_CLUSTERS_NUM_MAX) {
11351189
dev_err(dev, "Device cluster num %u is out of range for driver supports %d!\n",
1136-
hpre_cap[HPRE_CLUSTER_NUM_CAP_IDX].cap_val, HPRE_CLUSTERS_NUM_MAX);
1190+
clusters_num, HPRE_CLUSTERS_NUM_MAX);
11371191
return -EINVAL;
11381192
}
11391193

11401194
qm->cap_tables.dev_cap_table = hpre_cap;
1195+
qm->cap_tables.dev_cap_size = size;
11411196

11421197
return 0;
11431198
}
@@ -1184,7 +1239,7 @@ static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
11841239
return ret;
11851240
}
11861241

1187-
alg_msk = qm->cap_tables.dev_cap_table[HPRE_DEV_ALG_BITMAP_CAP_IDX].cap_val;
1242+
alg_msk = qm->cap_tables.dev_cap_table[HPRE_ALG_BITMAP].cap_val;
11881243
ret = hisi_qm_set_algs(qm, alg_msk, hpre_dev_algs, ARRAY_SIZE(hpre_dev_algs));
11891244
if (ret) {
11901245
pci_err(pdev, "Failed to set hpre algs!\n");
@@ -1200,10 +1255,13 @@ static int hpre_show_last_regs_init(struct hisi_qm *qm)
12001255
int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs);
12011256
struct qm_debug *debug = &qm->debug;
12021257
void __iomem *io_base;
1258+
u32 hpre_core_info;
12031259
u8 clusters_num;
12041260
int i, j, idx;
12051261

1206-
clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
1262+
hpre_core_info = qm->cap_tables.dev_cap_table[HPRE_CORE_INFO].cap_val;
1263+
clusters_num = (hpre_core_info >> hpre_basic_info[HPRE_CLUSTER_NUM_CAP].shift) &
1264+
hpre_basic_info[HPRE_CLUSTER_NUM_CAP].mask;
12071265
debug->last_words = kcalloc(cluster_dfx_regs_num * clusters_num +
12081266
com_dfx_regs_num, sizeof(unsigned int), GFP_KERNEL);
12091267
if (!debug->last_words)
@@ -1243,6 +1301,7 @@ static void hpre_show_last_dfx_regs(struct hisi_qm *qm)
12431301
struct qm_debug *debug = &qm->debug;
12441302
struct pci_dev *pdev = qm->pdev;
12451303
void __iomem *io_base;
1304+
u32 hpre_core_info;
12461305
u8 clusters_num;
12471306
int i, j, idx;
12481307
u32 val;
@@ -1258,7 +1317,9 @@ static void hpre_show_last_dfx_regs(struct hisi_qm *qm)
12581317
hpre_com_dfx_regs[i].name, debug->last_words[i], val);
12591318
}
12601319

1261-
clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
1320+
hpre_core_info = qm->cap_tables.dev_cap_table[HPRE_CORE_INFO].cap_val;
1321+
clusters_num = (hpre_core_info >> hpre_basic_info[HPRE_CLUSTER_NUM_CAP].shift) &
1322+
hpre_basic_info[HPRE_CLUSTER_NUM_CAP].mask;
12621323
for (i = 0; i < clusters_num; i++) {
12631324
io_base = qm->io_base + hpre_cluster_offsets[i];
12641325
for (j = 0; j < cluster_dfx_regs_num; j++) {

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