@@ -60,38 +60,65 @@ static struct snd_soc_dai_driver sc7180_lpass_cpu_dai_driver[] = {
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.probe = & asoc_qcom_lpass_cpu_dai_probe ,
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.ops = & asoc_qcom_lpass_cpu_dai_ops ,
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},
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+ [LPASS_DP_RX ] = {
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+ .id = LPASS_DP_RX ,
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+ .name = "Hdmi" ,
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+ .playback = {
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+ .stream_name = "Hdmi Playback" ,
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+ .formats = SNDRV_PCM_FMTBIT_S24 ,
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+ .rates = SNDRV_PCM_RATE_48000 ,
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+ .rate_min = 48000 ,
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+ .rate_max = 48000 ,
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+ .channels_min = 2 ,
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+ .channels_max = 2 ,
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+ },
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+ .ops = & asoc_qcom_lpass_hdmi_dai_ops ,
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+ },
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};
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static int sc7180_lpass_alloc_dma_channel (struct lpass_data * drvdata ,
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- int direction )
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+ int direction , unsigned int dai_id )
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{
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struct lpass_variant * v = drvdata -> variant ;
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int chan = 0 ;
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- if (direction == SNDRV_PCM_STREAM_PLAYBACK ) {
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- chan = find_first_zero_bit (& drvdata -> dma_ch_bit_map ,
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- v -> rdma_channels );
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+ if (dai_id == LPASS_DP_RX ) {
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+ if (direction == SNDRV_PCM_STREAM_PLAYBACK ) {
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+ chan = find_first_zero_bit (& drvdata -> hdmi_dma_ch_bit_map ,
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+ v -> hdmi_rdma_channels );
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+
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+ if (chan >= v -> hdmi_rdma_channels )
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+ return - EBUSY ;
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+ }
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+ set_bit (chan , & drvdata -> hdmi_dma_ch_bit_map );
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+ } else {
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+ if (direction == SNDRV_PCM_STREAM_PLAYBACK ) {
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+ chan = find_first_zero_bit (& drvdata -> dma_ch_bit_map ,
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+ v -> rdma_channels );
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if (chan >= v -> rdma_channels )
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return - EBUSY ;
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- } else {
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- chan = find_next_zero_bit (& drvdata -> dma_ch_bit_map ,
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+ } else {
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+ chan = find_next_zero_bit (& drvdata -> dma_ch_bit_map ,
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v -> wrdma_channel_start +
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v -> wrdma_channels ,
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v -> wrdma_channel_start );
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- if (chan >= v -> wrdma_channel_start + v -> wrdma_channels )
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- return - EBUSY ;
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- }
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-
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- set_bit (chan , & drvdata -> dma_ch_bit_map );
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+ if (chan >= v -> wrdma_channel_start + v -> wrdma_channels )
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+ return - EBUSY ;
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+ }
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+ set_bit (chan , & drvdata -> dma_ch_bit_map );
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+ }
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return chan ;
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}
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- static int sc7180_lpass_free_dma_channel (struct lpass_data * drvdata , int chan )
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+ static int sc7180_lpass_free_dma_channel (struct lpass_data * drvdata , int chan , unsigned int dai_id )
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{
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- clear_bit (chan , & drvdata -> dma_ch_bit_map );
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+ if (dai_id == LPASS_DP_RX )
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+ clear_bit (chan , & drvdata -> hdmi_dma_ch_bit_map );
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+ else
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+ clear_bit (chan , & drvdata -> dma_ch_bit_map );
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return 0 ;
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}
@@ -144,6 +171,9 @@ static struct lpass_variant sc7180_data = {
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.rdma_reg_base = 0xC000 ,
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.rdma_reg_stride = 0x1000 ,
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.rdma_channels = 5 ,
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+ .hdmi_rdma_reg_base = 0x64000 ,
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+ .hdmi_rdma_reg_stride = 0x1000 ,
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+ .hdmi_rdma_channels = 4 ,
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.dmactl_audif_start = 1 ,
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.wrdma_reg_base = 0x18000 ,
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.wrdma_reg_stride = 0x1000 ,
@@ -163,7 +193,7 @@ static struct lpass_variant sc7180_data = {
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.rdma_dyncclk = REG_FIELD_ID (0xC000 , 21 , 21 , 5 , 0x1000 ),
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.rdma_bursten = REG_FIELD_ID (0xC000 , 20 , 20 , 5 , 0x1000 ),
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.rdma_wpscnt = REG_FIELD_ID (0xC000 , 16 , 19 , 5 , 0x1000 ),
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- .rdma_intf = REG_FIELD_ID (0xC000 , 12 , 15 , 5 , 0x1000 ),
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+ .rdma_intf = REG_FIELD_ID (0xC000 , 12 , 15 , 5 , 0x1000 ),
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.rdma_fifowm = REG_FIELD_ID (0xC000 , 1 , 5 , 5 , 0x1000 ),
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.rdma_enable = REG_FIELD_ID (0xC000 , 0 , 0 , 5 , 0x1000 ),
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@@ -174,6 +204,64 @@ static struct lpass_variant sc7180_data = {
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.wrdma_fifowm = REG_FIELD_ID (0x18000 , 1 , 5 , 4 , 0x1000 ),
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.wrdma_enable = REG_FIELD_ID (0x18000 , 0 , 0 , 4 , 0x1000 ),
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+ .hdmi_tx_ctl_addr = 0x1000 ,
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+ .hdmi_legacy_addr = 0x1008 ,
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+ .hdmi_vbit_addr = 0x610c0 ,
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+ .hdmi_ch_lsb_addr = 0x61048 ,
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+ .hdmi_ch_msb_addr = 0x6104c ,
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+ .ch_stride = 0x8 ,
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+ .hdmi_parity_addr = 0x61034 ,
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+ .hdmi_dmactl_addr = 0x61038 ,
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+ .hdmi_dma_stride = 0x4 ,
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+ .hdmi_DP_addr = 0x610c8 ,
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+ .hdmi_sstream_addr = 0x6101c ,
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+ .hdmi_irq_reg_base = 0x63000 ,
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+ .hdmi_irq_ports = 1 ,
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+
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+ .hdmi_rdma_dyncclk = REG_FIELD_ID (0x64000 , 14 , 14 , 4 , 0x1000 ),
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+ .hdmi_rdma_bursten = REG_FIELD_ID (0x64000 , 13 , 13 , 4 , 0x1000 ),
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+ .hdmi_rdma_burst8 = REG_FIELD_ID (0x64000 , 15 , 15 , 4 , 0x1000 ),
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+ .hdmi_rdma_burst16 = REG_FIELD_ID (0x64000 , 16 , 16 , 4 , 0x1000 ),
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+ .hdmi_rdma_dynburst = REG_FIELD_ID (0x64000 , 18 , 18 , 4 , 0x1000 ),
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+ .hdmi_rdma_wpscnt = REG_FIELD_ID (0x64000 , 10 , 12 , 4 , 0x1000 ),
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+ .hdmi_rdma_fifowm = REG_FIELD_ID (0x64000 , 1 , 5 , 4 , 0x1000 ),
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+ .hdmi_rdma_enable = REG_FIELD_ID (0x64000 , 0 , 0 , 4 , 0x1000 ),
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+
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+ .sstream_en = REG_FIELD (0x6101c , 0 , 0 ),
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+ .dma_sel = REG_FIELD (0x6101c , 1 , 2 ),
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+ .auto_bbit_en = REG_FIELD (0x6101c , 3 , 3 ),
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+ .layout = REG_FIELD (0x6101c , 4 , 4 ),
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+ .layout_sp = REG_FIELD (0x6101c , 5 , 8 ),
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+ .set_sp_on_en = REG_FIELD (0x6101c , 10 , 10 ),
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+ .dp_audio = REG_FIELD (0x6101c , 11 , 11 ),
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+ .dp_staffing_en = REG_FIELD (0x6101c , 12 , 12 ),
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+ .dp_sp_b_hw_en = REG_FIELD (0x6101c , 13 , 13 ),
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+
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+ .mute = REG_FIELD (0x610c8 , 0 , 0 ),
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+ .as_sdp_cc = REG_FIELD (0x610c8 , 1 , 3 ),
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+ .as_sdp_ct = REG_FIELD (0x610c8 , 4 , 7 ),
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+ .aif_db4 = REG_FIELD (0x610c8 , 8 , 15 ),
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+ .frequency = REG_FIELD (0x610c8 , 16 , 21 ),
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+ .mst_index = REG_FIELD (0x610c8 , 28 , 29 ),
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+ .dptx_index = REG_FIELD (0x610c8 , 30 , 31 ),
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+
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+ .soft_reset = REG_FIELD (0x1000 , 31 , 31 ),
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+ .force_reset = REG_FIELD (0x1000 , 30 , 30 ),
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+
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+ .use_hw_chs = REG_FIELD (0x61038 , 0 , 0 ),
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+ .use_hw_usr = REG_FIELD (0x61038 , 1 , 1 ),
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+ .hw_chs_sel = REG_FIELD (0x61038 , 2 , 4 ),
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+ .hw_usr_sel = REG_FIELD (0x61038 , 5 , 6 ),
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+
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+ .replace_vbit = REG_FIELD (0x610c0 , 0 , 0 ),
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+ .vbit_stream = REG_FIELD (0x610c0 , 1 , 1 ),
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+
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+ .legacy_en = REG_FIELD (0x1008 , 0 , 0 ),
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+ .calc_en = REG_FIELD (0x61034 , 0 , 0 ),
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+ .lsb_bits = REG_FIELD (0x61048 , 0 , 31 ),
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+ .msb_bits = REG_FIELD (0x6104c , 0 , 31 ),
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+
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+
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.clk_name = (const char * []) {
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"pcnoc-sway-clk" ,
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"audio-core" ,
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