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171 | 171 | #define MLXPLAT_CPLD_NR_NONE -1
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172 | 172 | #define MLXPLAT_CPLD_PSU_DEFAULT_NR 10
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173 | 173 | #define MLXPLAT_CPLD_PSU_MSNXXXX_NR 4
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174 |
| -#define MLXPLAT_CPLD_PSU_MSNXXXX_NR2 3 |
175 | 174 | #define MLXPLAT_CPLD_FAN1_DEFAULT_NR 11
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176 | 175 | #define MLXPLAT_CPLD_FAN2_DEFAULT_NR 12
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177 | 176 | #define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13
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@@ -347,6 +346,15 @@ static struct i2c_board_info mlxplat_mlxcpld_pwr[] = {
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347 | 346 | },
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348 | 347 | };
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349 | 348 |
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| 349 | +static struct i2c_board_info mlxplat_mlxcpld_ext_pwr[] = { |
| 350 | + { |
| 351 | + I2C_BOARD_INFO("dps460", 0x5b), |
| 352 | + }, |
| 353 | + { |
| 354 | + I2C_BOARD_INFO("dps460", 0x5a), |
| 355 | + }, |
| 356 | +}; |
| 357 | + |
350 | 358 | static struct i2c_board_info mlxplat_mlxcpld_fan[] = {
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351 | 359 | {
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352 | 360 | I2C_BOARD_INFO("24c32", 0x50),
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@@ -921,15 +929,15 @@ static struct mlxreg_core_data mlxplat_mlxcpld_ext_pwr_items_data[] = {
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921 | 929 | .label = "pwr3",
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922 | 930 | .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
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923 | 931 | .mask = BIT(2),
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924 |
| - .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], |
925 |
| - .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR2, |
| 932 | + .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], |
| 933 | + .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, |
926 | 934 | },
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927 | 935 | {
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928 | 936 | .label = "pwr4",
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929 | 937 | .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
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930 | 938 | .mask = BIT(3),
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931 |
| - .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], |
932 |
| - .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR2, |
| 939 | + .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], |
| 940 | + .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, |
933 | 941 | },
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934 | 942 | };
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935 | 943 |
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