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81 | 81 | * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
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82 | 82 | * perf code: 0x03
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83 | 83 | * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL,
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84 |
| - * KBL,CML,ICL,TGL,RKL,ADL,RPL,MTL |
| 84 | + * KBL,CML,ICL,TGL,RKL |
85 | 85 | * Scope: Package (physical package)
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86 | 86 | * MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
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87 | 87 | * perf code: 0x04
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90 | 90 | * Scope: Package (physical package)
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91 | 91 | * MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
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92 | 92 | * perf code: 0x05
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93 |
| - * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL, |
94 |
| - * ADL,RPL,MTL |
| 93 | + * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL |
95 | 94 | * Scope: Package (physical package)
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96 | 95 | * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
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97 | 96 | * perf code: 0x06
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@@ -636,9 +635,7 @@ static const struct cstate_model adl_cstates __initconst = {
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636 | 635 | .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) |
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637 | 636 | BIT(PERF_CSTATE_PKG_C3_RES) |
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638 | 637 | BIT(PERF_CSTATE_PKG_C6_RES) |
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639 |
| - BIT(PERF_CSTATE_PKG_C7_RES) | |
640 | 638 | BIT(PERF_CSTATE_PKG_C8_RES) |
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641 |
| - BIT(PERF_CSTATE_PKG_C9_RES) | |
642 | 639 | BIT(PERF_CSTATE_PKG_C10_RES),
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643 | 640 | };
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644 | 641 |
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