@@ -769,7 +769,7 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
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struct adreno_gpu * adreno_gpu = & a6xx_gpu -> base ;
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const struct a6xx_info * a6xx_info = adreno_gpu -> info -> a6xx ;
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u32 fence_range_lower , fence_range_upper ;
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- u32 chipid , chipid_min = 0 ;
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+ u32 chipid = 0 ;
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int ret ;
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/* Vote veto for FAL10 */
@@ -831,27 +831,6 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
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if (a6xx_info -> gmu_chipid ) {
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chipid = a6xx_info -> gmu_chipid ;
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- /* NOTE: A730 may also fall in this if-condition with a future GMU fw update. */
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- } else if (adreno_is_a7xx (adreno_gpu ) && !adreno_is_a730 (adreno_gpu )) {
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- /* A7xx GPUs have obfuscated chip IDs. Use constant maj = 7 */
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- chipid = FIELD_PREP (GENMASK (31 , 24 ), 0x7 );
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-
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- /*
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- * The min part has a 1-1 mapping for each GPU SKU.
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- * This chipid that the GMU expects corresponds to the "GENX_Y_Z" naming,
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- * where X = major, Y = minor, Z = patchlevel, e.g. GEN7_2_1 for prod A740.
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- */
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- if (adreno_is_a740 (adreno_gpu ))
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- chipid_min = 2 ;
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- else if (adreno_is_a750 (adreno_gpu ))
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- chipid_min = 9 ;
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- else
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- return - EINVAL ;
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-
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- chipid |= FIELD_PREP (GENMASK (23 , 16 ), chipid_min );
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-
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- /* Get the patchid (which may vary) from the device tree */
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- chipid |= FIELD_PREP (GENMASK (15 , 8 ), adreno_patchid (adreno_gpu ));
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} else {
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/*
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* Note that the GMU has a slightly different layout for
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