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Enric Balletbo i Serrambgg
Enric Balletbo i Serra
authored and
mbgg
committed
soc / drm: mediatek: Move routing control to mmsys device
Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path(). Those functions will allow DRM driver and others to control the data path routing. Signed-off-by: Enric Balletbo i Serra <[email protected]> Reviewed-by: Matthias Brugger <[email protected]> Reviewed-by: CK Hu <[email protected]> Acked-by: CK Hu <[email protected]> Tested-by: Anders Roxell <[email protected]> Reviewed-by: Chun-Kuang Hu <[email protected]> Signed-off-by: Matthias Brugger <[email protected]>
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8 files changed

+318
-282
lines changed

8 files changed

+318
-282
lines changed

‎drivers/gpu/drm/mediatek/Kconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@ config DRM_MEDIATEK
1111
select DRM_MIPI_DSI
1212
select DRM_PANEL
1313
select MEMORY
14+
select MTK_MMSYS
1415
select MTK_SMI
1516
select VIDEOMODE_HELPERS
1617
help

‎drivers/gpu/drm/mediatek/mtk_drm_crtc.c

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
#include <linux/clk.h>
77
#include <linux/pm_runtime.h>
88
#include <linux/soc/mediatek/mtk-cmdq.h>
9+
#include <linux/soc/mediatek/mtk-mmsys.h>
910

1011
#include <asm/barrier.h>
1112
#include <soc/mediatek/smi.h>
@@ -28,7 +29,7 @@
2829
* @enabled: records whether crtc_enable succeeded
2930
* @planes: array of 4 drm_plane structures, one for each overlay plane
3031
* @pending_planes: whether any plane has pending changes to be applied
31-
* @config_regs: memory mapped mmsys configuration register space
32+
* @mmsys_dev: pointer to the mmsys device for configuration registers
3233
* @mutex: handle to one of the ten disp_mutex streams
3334
* @ddp_comp_nr: number of components in ddp_comp
3435
* @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
@@ -50,7 +51,7 @@ struct mtk_drm_crtc {
5051
u32 cmdq_event;
5152
#endif
5253

53-
void __iomem *config_regs;
54+
struct device *mmsys_dev;
5455
struct mtk_disp_mutex *mutex;
5556
unsigned int ddp_comp_nr;
5657
struct mtk_ddp_comp **ddp_comp;
@@ -300,9 +301,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
300301

301302
DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n");
302303
for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
303-
mtk_ddp_add_comp_to_path(mtk_crtc->config_regs,
304-
mtk_crtc->ddp_comp[i]->id,
305-
mtk_crtc->ddp_comp[i + 1]->id);
304+
mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
305+
mtk_crtc->ddp_comp[i]->id,
306+
mtk_crtc->ddp_comp[i + 1]->id);
306307
mtk_disp_mutex_add_comp(mtk_crtc->mutex,
307308
mtk_crtc->ddp_comp[i]->id);
308309
}
@@ -360,9 +361,9 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
360361
mtk_crtc->ddp_comp[i]->id);
361362
mtk_disp_mutex_disable(mtk_crtc->mutex);
362363
for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
363-
mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs,
364-
mtk_crtc->ddp_comp[i]->id,
365-
mtk_crtc->ddp_comp[i + 1]->id);
364+
mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
365+
mtk_crtc->ddp_comp[i]->id,
366+
mtk_crtc->ddp_comp[i + 1]->id);
366367
mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
367368
mtk_crtc->ddp_comp[i]->id);
368369
}
@@ -766,7 +767,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
766767
if (!mtk_crtc)
767768
return -ENOMEM;
768769

769-
mtk_crtc->config_regs = priv->config_regs;
770+
mtk_crtc->mmsys_dev = priv->mmsys_dev;
770771
mtk_crtc->ddp_comp_nr = path_len;
771772
mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
772773
sizeof(*mtk_crtc->ddp_comp),

‎drivers/gpu/drm/mediatek/mtk_drm_ddp.c

Lines changed: 0 additions & 256 deletions
Original file line numberDiff line numberDiff line change
@@ -13,26 +13,6 @@
1313
#include "mtk_drm_ddp.h"
1414
#include "mtk_drm_ddp_comp.h"
1515

16-
#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
17-
#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
18-
#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
19-
#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
20-
#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
21-
#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
22-
#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
23-
#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
24-
#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
25-
#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
26-
#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
27-
#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
28-
#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
29-
#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
30-
31-
#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
32-
#define DISP_REG_CONFIG_OUT_SEL 0x04c
33-
#define DISP_REG_CONFIG_DSI_SEL 0x050
34-
#define DISP_REG_CONFIG_DPI_SEL 0x064
35-
3616
#define MT2701_DISP_MUTEX0_MOD0 0x2c
3717
#define MT2701_DISP_MUTEX0_SOF0 0x30
3818

@@ -94,48 +74,6 @@
9474
#define MUTEX_SOF_DSI2 5
9575
#define MUTEX_SOF_DSI3 6
9676

97-
#define OVL0_MOUT_EN_COLOR0 0x1
98-
#define OD_MOUT_EN_RDMA0 0x1
99-
#define OD1_MOUT_EN_RDMA1 BIT(16)
100-
#define UFOE_MOUT_EN_DSI0 0x1
101-
#define COLOR0_SEL_IN_OVL0 0x1
102-
#define OVL1_MOUT_EN_COLOR1 0x1
103-
#define GAMMA_MOUT_EN_RDMA1 0x1
104-
#define RDMA0_SOUT_DPI0 0x2
105-
#define RDMA0_SOUT_DPI1 0x3
106-
#define RDMA0_SOUT_DSI1 0x1
107-
#define RDMA0_SOUT_DSI2 0x4
108-
#define RDMA0_SOUT_DSI3 0x5
109-
#define RDMA1_SOUT_DPI0 0x2
110-
#define RDMA1_SOUT_DPI1 0x3
111-
#define RDMA1_SOUT_DSI1 0x1
112-
#define RDMA1_SOUT_DSI2 0x4
113-
#define RDMA1_SOUT_DSI3 0x5
114-
#define RDMA2_SOUT_DPI0 0x2
115-
#define RDMA2_SOUT_DPI1 0x3
116-
#define RDMA2_SOUT_DSI1 0x1
117-
#define RDMA2_SOUT_DSI2 0x4
118-
#define RDMA2_SOUT_DSI3 0x5
119-
#define DPI0_SEL_IN_RDMA1 0x1
120-
#define DPI0_SEL_IN_RDMA2 0x3
121-
#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
122-
#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
123-
#define DSI0_SEL_IN_RDMA1 0x1
124-
#define DSI0_SEL_IN_RDMA2 0x4
125-
#define DSI1_SEL_IN_RDMA1 0x1
126-
#define DSI1_SEL_IN_RDMA2 0x4
127-
#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
128-
#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
129-
#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
130-
#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
131-
#define COLOR1_SEL_IN_OVL1 0x1
132-
133-
#define OVL_MOUT_EN_RDMA 0x1
134-
#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
135-
#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
136-
#define DSI_SEL_IN_BLS 0x0
137-
#define DPI_SEL_IN_BLS 0x0
138-
#define DSI_SEL_IN_RDMA 0x1
13977

14078
struct mtk_disp_mutex {
14179
int id;
@@ -246,200 +184,6 @@ static const struct mtk_ddp_data mt8173_ddp_driver_data = {
246184
.mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
247185
};
248186

249-
static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
250-
enum mtk_ddp_comp_id next,
251-
unsigned int *addr)
252-
{
253-
unsigned int value;
254-
255-
if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
256-
*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
257-
value = OVL0_MOUT_EN_COLOR0;
258-
} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
259-
*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
260-
value = OVL_MOUT_EN_RDMA;
261-
} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
262-
*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
263-
value = OD_MOUT_EN_RDMA0;
264-
} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
265-
*addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
266-
value = UFOE_MOUT_EN_DSI0;
267-
} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
268-
*addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
269-
value = OVL1_MOUT_EN_COLOR1;
270-
} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
271-
*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
272-
value = GAMMA_MOUT_EN_RDMA1;
273-
} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
274-
*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
275-
value = OD1_MOUT_EN_RDMA1;
276-
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
277-
*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
278-
value = RDMA0_SOUT_DPI0;
279-
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
280-
*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
281-
value = RDMA0_SOUT_DPI1;
282-
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
283-
*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
284-
value = RDMA0_SOUT_DSI1;
285-
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
286-
*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
287-
value = RDMA0_SOUT_DSI2;
288-
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
289-
*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
290-
value = RDMA0_SOUT_DSI3;
291-
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
292-
*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
293-
value = RDMA1_SOUT_DSI1;
294-
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
295-
*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
296-
value = RDMA1_SOUT_DSI2;
297-
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
298-
*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
299-
value = RDMA1_SOUT_DSI3;
300-
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
301-
*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
302-
value = RDMA1_SOUT_DPI0;
303-
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
304-
*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
305-
value = RDMA1_SOUT_DPI1;
306-
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
307-
*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
308-
value = RDMA2_SOUT_DPI0;
309-
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
310-
*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
311-
value = RDMA2_SOUT_DPI1;
312-
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
313-
*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
314-
value = RDMA2_SOUT_DSI1;
315-
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
316-
*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
317-
value = RDMA2_SOUT_DSI2;
318-
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
319-
*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
320-
value = RDMA2_SOUT_DSI3;
321-
} else {
322-
value = 0;
323-
}
324-
325-
return value;
326-
}
327-
328-
static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
329-
enum mtk_ddp_comp_id next,
330-
unsigned int *addr)
331-
{
332-
unsigned int value;
333-
334-
if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
335-
*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
336-
value = COLOR0_SEL_IN_OVL0;
337-
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
338-
*addr = DISP_REG_CONFIG_DPI_SEL_IN;
339-
value = DPI0_SEL_IN_RDMA1;
340-
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
341-
*addr = DISP_REG_CONFIG_DPI_SEL_IN;
342-
value = DPI1_SEL_IN_RDMA1;
343-
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
344-
*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
345-
value = DSI0_SEL_IN_RDMA1;
346-
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
347-
*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
348-
value = DSI1_SEL_IN_RDMA1;
349-
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
350-
*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
351-
value = DSI2_SEL_IN_RDMA1;
352-
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
353-
*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
354-
value = DSI3_SEL_IN_RDMA1;
355-
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
356-
*addr = DISP_REG_CONFIG_DPI_SEL_IN;
357-
value = DPI0_SEL_IN_RDMA2;
358-
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
359-
*addr = DISP_REG_CONFIG_DPI_SEL_IN;
360-
value = DPI1_SEL_IN_RDMA2;
361-
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
362-
*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
363-
value = DSI0_SEL_IN_RDMA2;
364-
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
365-
*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
366-
value = DSI1_SEL_IN_RDMA2;
367-
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
368-
*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
369-
value = DSI2_SEL_IN_RDMA2;
370-
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
371-
*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
372-
value = DSI3_SEL_IN_RDMA2;
373-
} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
374-
*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
375-
value = COLOR1_SEL_IN_OVL1;
376-
} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
377-
*addr = DISP_REG_CONFIG_DSI_SEL;
378-
value = DSI_SEL_IN_BLS;
379-
} else {
380-
value = 0;
381-
}
382-
383-
return value;
384-
}
385-
386-
static void mtk_ddp_sout_sel(void __iomem *config_regs,
387-
enum mtk_ddp_comp_id cur,
388-
enum mtk_ddp_comp_id next)
389-
{
390-
if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
391-
writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
392-
config_regs + DISP_REG_CONFIG_OUT_SEL);
393-
} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
394-
writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
395-
config_regs + DISP_REG_CONFIG_OUT_SEL);
396-
writel_relaxed(DSI_SEL_IN_RDMA,
397-
config_regs + DISP_REG_CONFIG_DSI_SEL);
398-
writel_relaxed(DPI_SEL_IN_BLS,
399-
config_regs + DISP_REG_CONFIG_DPI_SEL);
400-
}
401-
}
402-
403-
void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
404-
enum mtk_ddp_comp_id cur,
405-
enum mtk_ddp_comp_id next)
406-
{
407-
unsigned int addr, value, reg;
408-
409-
value = mtk_ddp_mout_en(cur, next, &addr);
410-
if (value) {
411-
reg = readl_relaxed(config_regs + addr) | value;
412-
writel_relaxed(reg, config_regs + addr);
413-
}
414-
415-
mtk_ddp_sout_sel(config_regs, cur, next);
416-
417-
value = mtk_ddp_sel_in(cur, next, &addr);
418-
if (value) {
419-
reg = readl_relaxed(config_regs + addr) | value;
420-
writel_relaxed(reg, config_regs + addr);
421-
}
422-
}
423-
424-
void mtk_ddp_remove_comp_from_path(void __iomem *config_regs,
425-
enum mtk_ddp_comp_id cur,
426-
enum mtk_ddp_comp_id next)
427-
{
428-
unsigned int addr, value, reg;
429-
430-
value = mtk_ddp_mout_en(cur, next, &addr);
431-
if (value) {
432-
reg = readl_relaxed(config_regs + addr) & ~value;
433-
writel_relaxed(reg, config_regs + addr);
434-
}
435-
436-
value = mtk_ddp_sel_in(cur, next, &addr);
437-
if (value) {
438-
reg = readl_relaxed(config_regs + addr) & ~value;
439-
writel_relaxed(reg, config_regs + addr);
440-
}
441-
}
442-
443187
struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id)
444188
{
445189
struct mtk_ddp *ddp = dev_get_drvdata(dev);

‎drivers/gpu/drm/mediatek/mtk_drm_ddp.h

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -12,13 +12,6 @@ struct regmap;
1212
struct device;
1313
struct mtk_disp_mutex;
1414

15-
void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
16-
enum mtk_ddp_comp_id cur,
17-
enum mtk_ddp_comp_id next);
18-
void mtk_ddp_remove_comp_from_path(void __iomem *config_regs,
19-
enum mtk_ddp_comp_id cur,
20-
enum mtk_ddp_comp_id next);
21-
2215
struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id);
2316
int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex);
2417
void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,

‎drivers/gpu/drm/mediatek/mtk_drm_drv.c

Lines changed: 5 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@
1010
#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/pm_runtime.h>
13+
#include <linux/soc/mediatek/mtk-mmsys.h>
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#include <linux/dma-mapping.h>
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#include <drm/drm_atomic.h>
@@ -425,7 +426,6 @@ static int mtk_drm_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mtk_drm_private *private;
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struct resource *mem;
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struct device_node *node;
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struct component_match *match = NULL;
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int ret;
@@ -436,14 +436,10 @@ static int mtk_drm_probe(struct platform_device *pdev)
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return -ENOMEM;
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private->data = of_device_get_match_data(dev);
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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private->config_regs = devm_ioremap_resource(dev, mem);
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if (IS_ERR(private->config_regs)) {
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ret = PTR_ERR(private->config_regs);
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dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
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ret);
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return ret;
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private->mmsys_dev = dev->parent;
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if (!private->mmsys_dev) {
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dev_err(dev, "Failed to get MMSYS device\n");
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return -ENODEV;
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}
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/* Iterate over sibling DISP function blocks */

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