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bjorn-helgaasbjorn-helgaas
committed
Merge branch 'pci/endpoint'
- For fixed-size BARs, retain both the actual size and the possibly larger size allocated to accommodate iATU alignment requirements (Jerome Brunet) - Simplify ctrl/SPAD space allocation and avoid allocating more space than needed (Jerome Brunet) - Correct MSI-X PBA offset calculations for DesignWare and Cadence endpoint controllers (Niklas Cassel) - Align the return value (number of interrupts) encoding for pci_epc_get_msi()/pci_epc_ops::get_msi() and pci_epc_get_msix()/pci_epc_ops::get_msix() (Niklas Cassel) - Align the nr_irqs parameter encoding for pci_epc_set_msi()/pci_epc_ops::set_msi() and pci_epc_set_msix()/pci_epc_ops::set_msix() (Niklas Cassel) * pci/endpoint: PCI: endpoint: Align pci_epc_set_msix(), pci_epc_ops::set_msix() nr_irqs encoding PCI: endpoint: Align pci_epc_set_msi(), pci_epc_ops::set_msi() nr_irqs encoding PCI: endpoint: Align pci_epc_get_msix(), pci_epc_ops::get_msix() return value encoding PCI: endpoint: Align pci_epc_get_msi(), pci_epc_ops::get_msi() return value encoding PCI: cadence-ep: Correct PBA offset in .set_msix() callback PCI: dwc: ep: Correct PBA offset in .set_msix() callback PCI: endpoint: pci-epf-vntb: Simplify ctrl/SPAD space allocation PCI: endpoint: Retain fixed-size BAR size as well as aligned size
2 parents 014dbfe + de0321b commit 2ce7387

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9 files changed

+60
-74
lines changed

9 files changed

+60
-74
lines changed

‎drivers/pci/controller/cadence/pcie-cadence-ep.c

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -220,10 +220,11 @@ static void cdns_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, u8 vfn,
220220
clear_bit(r, &ep->ob_region_map);
221221
}
222222

223-
static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 mmc)
223+
static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 nr_irqs)
224224
{
225225
struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
226226
struct cdns_pcie *pcie = &ep->pcie;
227+
u8 mmc = order_base_2(nr_irqs);
227228
u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
228229
u16 flags;
229230

@@ -262,7 +263,7 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn)
262263
*/
263264
mme = FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags);
264265

265-
return mme;
266+
return 1 << mme;
266267
}
267268

268269
static int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
@@ -281,12 +282,11 @@ static int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
281282

282283
val &= PCI_MSIX_FLAGS_QSIZE;
283284

284-
return val;
285+
return val + 1;
285286
}
286287

287288
static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn,
288-
u16 interrupts, enum pci_barno bir,
289-
u32 offset)
289+
u16 nr_irqs, enum pci_barno bir, u32 offset)
290290
{
291291
struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
292292
struct cdns_pcie *pcie = &ep->pcie;
@@ -298,7 +298,7 @@ static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn,
298298
reg = cap + PCI_MSIX_FLAGS;
299299
val = cdns_pcie_ep_fn_readw(pcie, fn, reg);
300300
val &= ~PCI_MSIX_FLAGS_QSIZE;
301-
val |= interrupts;
301+
val |= nr_irqs - 1; /* encoded as N-1 */
302302
cdns_pcie_ep_fn_writew(pcie, fn, reg, val);
303303

304304
/* Set MSI-X BAR and offset */
@@ -308,7 +308,7 @@ static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn,
308308

309309
/* Set PBA BAR and offset. BAR must match MSI-X BAR */
310310
reg = cap + PCI_MSIX_PBA;
311-
val = (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir;
311+
val = (offset + (nr_irqs * PCI_MSIX_ENTRY_SIZE)) | bir;
312312
cdns_pcie_ep_fn_writel(pcie, fn, reg, val);
313313

314314
return 0;

‎drivers/pci/controller/dwc/pcie-designware-ep.c

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -532,15 +532,16 @@ static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
532532

533533
val = FIELD_GET(PCI_MSI_FLAGS_QSIZE, val);
534534

535-
return val;
535+
return 1 << val;
536536
}
537537

538538
static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
539-
u8 interrupts)
539+
u8 nr_irqs)
540540
{
541541
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
542542
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
543543
struct dw_pcie_ep_func *ep_func;
544+
u8 mmc = order_base_2(nr_irqs);
544545
u32 val, reg;
545546

546547
ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
@@ -550,7 +551,7 @@ static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
550551
reg = ep_func->msi_cap + PCI_MSI_FLAGS;
551552
val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
552553
val &= ~PCI_MSI_FLAGS_QMASK;
553-
val |= FIELD_PREP(PCI_MSI_FLAGS_QMASK, interrupts);
554+
val |= FIELD_PREP(PCI_MSI_FLAGS_QMASK, mmc);
554555
dw_pcie_dbi_ro_wr_en(pci);
555556
dw_pcie_ep_writew_dbi(ep, func_no, reg, val);
556557
dw_pcie_dbi_ro_wr_dis(pci);
@@ -575,11 +576,11 @@ static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
575576

576577
val &= PCI_MSIX_FLAGS_QSIZE;
577578

578-
return val;
579+
return val + 1;
579580
}
580581

581582
static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
582-
u16 interrupts, enum pci_barno bir, u32 offset)
583+
u16 nr_irqs, enum pci_barno bir, u32 offset)
583584
{
584585
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
585586
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
@@ -595,15 +596,15 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
595596
reg = ep_func->msix_cap + PCI_MSIX_FLAGS;
596597
val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
597598
val &= ~PCI_MSIX_FLAGS_QSIZE;
598-
val |= interrupts;
599+
val |= nr_irqs - 1; /* encoded as N-1 */
599600
dw_pcie_writew_dbi(pci, reg, val);
600601

601602
reg = ep_func->msix_cap + PCI_MSIX_TABLE;
602603
val = offset | bir;
603604
dw_pcie_ep_writel_dbi(ep, func_no, reg, val);
604605

605606
reg = ep_func->msix_cap + PCI_MSIX_PBA;
606-
val = (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir;
607+
val = (offset + (nr_irqs * PCI_MSIX_ENTRY_SIZE)) | bir;
607608
dw_pcie_ep_writel_dbi(ep, func_no, reg, val);
608609

609610
dw_pcie_dbi_ro_wr_dis(pci);

‎drivers/pci/controller/pcie-rcar-ep.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -256,15 +256,15 @@ static void rcar_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, u8 vfn,
256256
clear_bit(atu_index + 1, ep->ib_window_map);
257257
}
258258

259-
static int rcar_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn,
260-
u8 interrupts)
259+
static int rcar_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 nr_irqs)
261260
{
262261
struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
263262
struct rcar_pcie *pcie = &ep->pcie;
263+
u8 mmc = order_base_2(nr_irqs);
264264
u32 flags;
265265

266266
flags = rcar_pci_read_reg(pcie, MSICAP(fn));
267-
flags |= interrupts << MSICAP0_MMESCAP_OFFSET;
267+
flags |= mmc << MSICAP0_MMESCAP_OFFSET;
268268
rcar_pci_write_reg(pcie, flags, MSICAP(fn));
269269

270270
return 0;
@@ -280,7 +280,7 @@ static int rcar_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn)
280280
if (!(flags & MSICAP0_MSIE))
281281
return -EINVAL;
282282

283-
return ((flags & MSICAP0_MMESE_MASK) >> MSICAP0_MMESE_OFFSET);
283+
return 1 << ((flags & MSICAP0_MMESE_MASK) >> MSICAP0_MMESE_OFFSET);
284284
}
285285

286286
static int rcar_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn,

‎drivers/pci/controller/pcie-rockchip-ep.c

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -308,18 +308,19 @@ static void rockchip_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, u8 vfn,
308308
}
309309

310310
static int rockchip_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn,
311-
u8 multi_msg_cap)
311+
u8 nr_irqs)
312312
{
313313
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
314314
struct rockchip_pcie *rockchip = &ep->rockchip;
315+
u8 mmc = order_base_2(nr_irqs);
315316
u32 flags;
316317

317318
flags = rockchip_pcie_read(rockchip,
318319
ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
319320
ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
320321
flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK;
321322
flags |=
322-
(multi_msg_cap << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) |
323+
(mmc << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) |
323324
(PCI_MSI_FLAGS_64BIT << ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET);
324325
flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP;
325326
rockchip_pcie_write(rockchip, flags,
@@ -340,8 +341,8 @@ static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn)
340341
if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME))
341342
return -EINVAL;
342343

343-
return ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >>
344-
ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET);
344+
return 1 << ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >>
345+
ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET);
345346
}
346347

347348
static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn,

‎drivers/pci/endpoint/functions/pci-epf-vntb.c

Lines changed: 3 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -408,11 +408,9 @@ static void epf_ntb_config_spad_bar_free(struct epf_ntb *ntb)
408408
*/
409409
static int epf_ntb_config_spad_bar_alloc(struct epf_ntb *ntb)
410410
{
411-
size_t align;
412411
enum pci_barno barno;
413412
struct epf_ntb_ctrl *ctrl;
414413
u32 spad_size, ctrl_size;
415-
u64 size;
416414
struct pci_epf *epf = ntb->epf;
417415
struct device *dev = &epf->dev;
418416
u32 spad_count;
@@ -422,31 +420,13 @@ static int epf_ntb_config_spad_bar_alloc(struct epf_ntb *ntb)
422420
epf->func_no,
423421
epf->vfunc_no);
424422
barno = ntb->epf_ntb_bar[BAR_CONFIG];
425-
size = epc_features->bar[barno].fixed_size;
426-
align = epc_features->align;
427-
428-
if ((!IS_ALIGNED(size, align)))
429-
return -EINVAL;
430-
431423
spad_count = ntb->spad_count;
432424

433-
ctrl_size = sizeof(struct epf_ntb_ctrl);
425+
ctrl_size = ALIGN(sizeof(struct epf_ntb_ctrl), sizeof(u32));
434426
spad_size = 2 * spad_count * sizeof(u32);
435427

436-
if (!align) {
437-
ctrl_size = roundup_pow_of_two(ctrl_size);
438-
spad_size = roundup_pow_of_two(spad_size);
439-
} else {
440-
ctrl_size = ALIGN(ctrl_size, align);
441-
spad_size = ALIGN(spad_size, align);
442-
}
443-
444-
if (!size)
445-
size = ctrl_size + spad_size;
446-
else if (size < ctrl_size + spad_size)
447-
return -EINVAL;
448-
449-
base = pci_epf_alloc_space(epf, size, barno, epc_features, 0);
428+
base = pci_epf_alloc_space(epf, ctrl_size + spad_size,
429+
barno, epc_features, 0);
450430
if (!base) {
451431
dev_err(dev, "Config/Status/SPAD alloc region fail\n");
452432
return -ENOMEM;

‎drivers/pci/endpoint/pci-epc-core.c

Lines changed: 10 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -293,8 +293,6 @@ int pci_epc_get_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
293293
if (interrupt < 0)
294294
return 0;
295295

296-
interrupt = 1 << interrupt;
297-
298296
return interrupt;
299297
}
300298
EXPORT_SYMBOL_GPL(pci_epc_get_msi);
@@ -304,28 +302,25 @@ EXPORT_SYMBOL_GPL(pci_epc_get_msi);
304302
* @epc: the EPC device on which MSI has to be configured
305303
* @func_no: the physical endpoint function number in the EPC device
306304
* @vfunc_no: the virtual endpoint function number in the physical function
307-
* @interrupts: number of MSI interrupts required by the EPF
305+
* @nr_irqs: number of MSI interrupts required by the EPF
308306
*
309307
* Invoke to set the required number of MSI interrupts.
310308
*/
311-
int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no, u8 interrupts)
309+
int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no, u8 nr_irqs)
312310
{
313311
int ret;
314-
u8 encode_int;
315312

316313
if (!pci_epc_function_is_valid(epc, func_no, vfunc_no))
317314
return -EINVAL;
318315

319-
if (interrupts < 1 || interrupts > 32)
316+
if (nr_irqs < 1 || nr_irqs > 32)
320317
return -EINVAL;
321318

322319
if (!epc->ops->set_msi)
323320
return 0;
324321

325-
encode_int = order_base_2(interrupts);
326-
327322
mutex_lock(&epc->lock);
328-
ret = epc->ops->set_msi(epc, func_no, vfunc_no, encode_int);
323+
ret = epc->ops->set_msi(epc, func_no, vfunc_no, nr_irqs);
329324
mutex_unlock(&epc->lock);
330325

331326
return ret;
@@ -357,7 +352,7 @@ int pci_epc_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
357352
if (interrupt < 0)
358353
return 0;
359354

360-
return interrupt + 1;
355+
return interrupt;
361356
}
362357
EXPORT_SYMBOL_GPL(pci_epc_get_msix);
363358

@@ -366,29 +361,28 @@ EXPORT_SYMBOL_GPL(pci_epc_get_msix);
366361
* @epc: the EPC device on which MSI-X has to be configured
367362
* @func_no: the physical endpoint function number in the EPC device
368363
* @vfunc_no: the virtual endpoint function number in the physical function
369-
* @interrupts: number of MSI-X interrupts required by the EPF
364+
* @nr_irqs: number of MSI-X interrupts required by the EPF
370365
* @bir: BAR where the MSI-X table resides
371366
* @offset: Offset pointing to the start of MSI-X table
372367
*
373368
* Invoke to set the required number of MSI-X interrupts.
374369
*/
375-
int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
376-
u16 interrupts, enum pci_barno bir, u32 offset)
370+
int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no, u16 nr_irqs,
371+
enum pci_barno bir, u32 offset)
377372
{
378373
int ret;
379374

380375
if (!pci_epc_function_is_valid(epc, func_no, vfunc_no))
381376
return -EINVAL;
382377

383-
if (interrupts < 1 || interrupts > 2048)
378+
if (nr_irqs < 1 || nr_irqs > 2048)
384379
return -EINVAL;
385380

386381
if (!epc->ops->set_msix)
387382
return 0;
388383

389384
mutex_lock(&epc->lock);
390-
ret = epc->ops->set_msix(epc, func_no, vfunc_no, interrupts - 1, bir,
391-
offset);
385+
ret = epc->ops->set_msix(epc, func_no, vfunc_no, nr_irqs, bir, offset);
392386
mutex_unlock(&epc->lock);
393387

394388
return ret;

‎drivers/pci/endpoint/pci-epf-core.c

Lines changed: 15 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -236,12 +236,13 @@ void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar,
236236
}
237237

238238
dev = epc->dev.parent;
239-
dma_free_coherent(dev, epf_bar[bar].size, addr,
239+
dma_free_coherent(dev, epf_bar[bar].aligned_size, addr,
240240
epf_bar[bar].phys_addr);
241241

242242
epf_bar[bar].phys_addr = 0;
243243
epf_bar[bar].addr = NULL;
244244
epf_bar[bar].size = 0;
245+
epf_bar[bar].aligned_size = 0;
245246
epf_bar[bar].barno = 0;
246247
epf_bar[bar].flags = 0;
247248
}
@@ -264,7 +265,7 @@ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar,
264265
enum pci_epc_interface_type type)
265266
{
266267
u64 bar_fixed_size = epc_features->bar[bar].fixed_size;
267-
size_t align = epc_features->align;
268+
size_t aligned_size, align = epc_features->align;
268269
struct pci_epf_bar *epf_bar;
269270
dma_addr_t phys_addr;
270271
struct pci_epc *epc;
@@ -285,12 +286,18 @@ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar,
285286
return NULL;
286287
}
287288
size = bar_fixed_size;
289+
} else {
290+
/* BAR size must be power of two */
291+
size = roundup_pow_of_two(size);
288292
}
289293

290-
if (align)
291-
size = ALIGN(size, align);
292-
else
293-
size = roundup_pow_of_two(size);
294+
/*
295+
* Allocate enough memory to accommodate the iATU alignment
296+
* requirement. In most cases, this will be the same as .size but
297+
* it might be different if, for example, the fixed size of a BAR
298+
* is smaller than align.
299+
*/
300+
aligned_size = align ? ALIGN(size, align) : size;
294301

295302
if (type == PRIMARY_INTERFACE) {
296303
epc = epf->epc;
@@ -301,7 +308,7 @@ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar,
301308
}
302309

303310
dev = epc->dev.parent;
304-
space = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL);
311+
space = dma_alloc_coherent(dev, aligned_size, &phys_addr, GFP_KERNEL);
305312
if (!space) {
306313
dev_err(dev, "failed to allocate mem space\n");
307314
return NULL;
@@ -310,6 +317,7 @@ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar,
310317
epf_bar[bar].phys_addr = phys_addr;
311318
epf_bar[bar].addr = space;
312319
epf_bar[bar].size = size;
320+
epf_bar[bar].aligned_size = aligned_size;
313321
epf_bar[bar].barno = bar;
314322
if (upper_32_bits(size) || epc_features->bar[bar].only_64bit)
315323
epf_bar[bar].flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;

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