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Merge tag 'drm-fixes-2023-03-17' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie: "Seems like a pretty regular rc3, i915 and amdgpu with the usual selection of fixes, then a scattering of fixes across misc drivers and other areas: accel: - build fix for accel edid: - fix info leak in edid ttm: - fix NULL ptr deref - reference counting fix i915: - Fix hwmon PL1 power limit enabling - Fix audio ELD handling for DP MST - Fix PSR io and wake line calculations - Fix DG2 HDMI modes with 267.30 and 319.89 MHz pixel clocks - Fix SSEU subslice out-of-bounds access - Fix misuse of non-idle barriers as fence trackers amdgpu: - SMU 13 update - RDNA2 suspend/resume fix when overclocking is enabled - SRIOV VCN fixes - HDCP suspend/resume fix - Fix drm polling splat regression - Fix dirty rectangle tracking for PSR - Fix vangogh regression on certain BIOSes - Misc display fixes - Suspend/resume IOMMU regression fix amdkfd: - Fix BO offset for multi-VMA page migration - Fix a possible double free - Fix potential use after free - Fix process cleanup on module exit bridge: - fix returned array size name documentation fbdev: - ref-counting fix for fbdev deferred I/O virtio: - dma sync fix shmem-helper: - error path fix msm: - shrinker blocking fix panfrost: - shrinker rpm fix chipsfb: - fix error code meson: - fix 1px pink line - fix regulator interaction sun4i: - fix missing component unbind" * tag 'drm-fixes-2023-03-17' of git://anongit.freedesktop.org/drm/drm: (38 commits) drm/ttm: drop extra ttm_bo_put in ttm_bo_cleanup_refs drm/amdgpu: Don't resume IOMMU after incomplete init drm/amdkfd: Fixed kfd_process cleanup on module exit. drm/amd/display: disconnect MPCC only on OTG change drm/amd/display: Fix DP MST sinks removal issue drm/amd/display: Do not set DRR on pipe Commit drm/amd/display: Remove OTG DIV register write for Virtual signals. drm/meson: dw-hdmi: Fix devm_regulator_*get_enable*() conversion again drm/bridge: Fix returned array size name for atomic_get_input_bus_fmts kdoc drm/amdgpu/vcn: Disable indirect SRAM on Vangogh broken BIOSes drm/amdgpu/nv: fix codec array for SR_IOV drm/amd/display: Write to correct dirty_rect drm/amdgpu: move poll enabled/disable into non DC path drm/amd/display: Fix HDCP failing to enable after suspend drm/amdkfd: fix potential kgd_mem UAFs drm/amdgpu/vcn: custom video info caps for sriov drm/amd/pm: Fix sienna cichlid incorrect OD volage after resume drm/amd/pm: bump SMU 13.0.4 driver_if header version drm/amdkfd: fix a potential double free in pqm_create_queue drm/amdkfd: Get prange->offset after svm_range_vram_node_new ...
2 parents 7622976 + c00133a commit 2cf5a40

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47 files changed

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lines changed

‎drivers/accel/Makefile

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
11
# SPDX-License-Identifier: GPL-2.0-only
22

3-
obj-y += habanalabs/
4-
obj-y += ivpu/
3+
obj-$(CONFIG_DRM_ACCEL_HABANALABS) += habanalabs/
4+
obj-$(CONFIG_DRM_ACCEL_IVPU) += ivpu/

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4145,8 +4145,6 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
41454145
if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3))
41464146
DRM_WARN("smart shift update failed\n");
41474147

4148-
drm_kms_helper_poll_disable(dev);
4149-
41504148
if (fbcon)
41514149
drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
41524150

@@ -4243,8 +4241,6 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
42434241
if (fbcon)
42444242
drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false);
42454243

4246-
drm_kms_helper_poll_enable(dev);
4247-
42484244
amdgpu_ras_resume(adev);
42494245

42504246
if (adev->mode_info.num_crtc) {

‎drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1618,6 +1618,8 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev)
16181618
struct drm_connector_list_iter iter;
16191619
int r;
16201620

1621+
drm_kms_helper_poll_disable(dev);
1622+
16211623
/* turn off display hw */
16221624
drm_modeset_lock_all(dev);
16231625
drm_connector_list_iter_begin(dev, &iter);
@@ -1694,6 +1696,8 @@ int amdgpu_display_resume_helper(struct amdgpu_device *adev)
16941696

16951697
drm_modeset_unlock_all(dev);
16961698

1699+
drm_kms_helper_poll_enable(dev);
1700+
16971701
return 0;
16981702
}
16991703

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@
2626

2727
#include <linux/firmware.h>
2828
#include <linux/module.h>
29+
#include <linux/dmi.h>
2930
#include <linux/pci.h>
3031
#include <linux/debugfs.h>
3132
#include <drm/drm_drv.h>
@@ -114,6 +115,24 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
114115
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
115116
adev->vcn.indirect_sram = true;
116117

118+
/*
119+
* Some Steam Deck's BIOS versions are incompatible with the
120+
* indirect SRAM mode, leading to amdgpu being unable to get
121+
* properly probed (and even potentially crashing the kernel).
122+
* Hence, check for these versions here - notice this is
123+
* restricted to Vangogh (Deck's APU).
124+
*/
125+
if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 2)) {
126+
const char *bios_ver = dmi_get_system_info(DMI_BIOS_VERSION);
127+
128+
if (bios_ver && (!strncmp("F7A0113", bios_ver, 7) ||
129+
!strncmp("F7A0114", bios_ver, 7))) {
130+
adev->vcn.indirect_sram = false;
131+
dev_info(adev->dev,
132+
"Steam Deck quirk: indirect SRAM disabled on BIOS %s\n", bios_ver);
133+
}
134+
}
135+
117136
hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
118137
adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
119138

‎drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -124,6 +124,8 @@ enum AMDGIM_FEATURE_FLAG {
124124
AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
125125
/* Indirect Reg Access enabled */
126126
AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5),
127+
/* AV1 Support MODE*/
128+
AMDGIM_FEATURE_AV1_SUPPORT = (1 << 6),
127129
};
128130

129131
enum AMDGIM_REG_ACCESS_FLAG {
@@ -322,6 +324,8 @@ static inline bool is_virtual_machine(void)
322324
((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)
323325
#define amdgpu_sriov_is_normal(adev) \
324326
((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))
327+
#define amdgpu_sriov_is_av1_support(adev) \
328+
((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT)
325329
bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
326330
void amdgpu_virt_init_setting(struct amdgpu_device *adev);
327331
void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,

‎drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,8 @@ union amd_sriov_msg_feature_flags {
9393
uint32_t mm_bw_management : 1;
9494
uint32_t pp_one_vf_mode : 1;
9595
uint32_t reg_indirect_acc : 1;
96-
uint32_t reserved : 26;
96+
uint32_t av1_support : 1;
97+
uint32_t reserved : 25;
9798
} flags;
9899
uint32_t all;
99100
};

‎drivers/gpu/drm/amd/amdgpu/nv.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1055,8 +1055,8 @@ static int nv_common_late_init(void *handle)
10551055
amdgpu_virt_update_sriov_video_codec(adev,
10561056
sriov_sc_video_codecs_encode_array,
10571057
ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
1058-
sriov_sc_video_codecs_decode_array_vcn1,
1059-
ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1));
1058+
sriov_sc_video_codecs_decode_array_vcn0,
1059+
ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0));
10601060
}
10611061
}
10621062

‎drivers/gpu/drm/amd/amdgpu/soc21.c

Lines changed: 93 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -102,6 +102,59 @@ static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 =
102102
.codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1,
103103
};
104104

105+
/* SRIOV SOC21, not const since data is controlled by host */
106+
static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
107+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
108+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
109+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
110+
};
111+
112+
static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
113+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
114+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
115+
};
116+
117+
static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = {
118+
.codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
119+
.codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
120+
};
121+
122+
static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = {
123+
.codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
124+
.codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
125+
};
126+
127+
static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = {
128+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
129+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
130+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
131+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
132+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
133+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
134+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
135+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
136+
};
137+
138+
static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = {
139+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
140+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
141+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
142+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
143+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
144+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
145+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
146+
};
147+
148+
static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = {
149+
.codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0),
150+
.codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
151+
};
152+
153+
static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = {
154+
.codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1),
155+
.codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
156+
};
157+
105158
static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
106159
const struct amdgpu_video_codecs **codecs)
107160
{
@@ -112,16 +165,31 @@ static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
112165
case IP_VERSION(4, 0, 0):
113166
case IP_VERSION(4, 0, 2):
114167
case IP_VERSION(4, 0, 4):
115-
if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
116-
if (encode)
117-
*codecs = &vcn_4_0_0_video_codecs_encode_vcn1;
118-
else
119-
*codecs = &vcn_4_0_0_video_codecs_decode_vcn1;
168+
if (amdgpu_sriov_vf(adev)) {
169+
if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
170+
!amdgpu_sriov_is_av1_support(adev)) {
171+
if (encode)
172+
*codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1;
173+
else
174+
*codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1;
175+
} else {
176+
if (encode)
177+
*codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0;
178+
else
179+
*codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0;
180+
}
120181
} else {
121-
if (encode)
122-
*codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
123-
else
124-
*codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
182+
if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) {
183+
if (encode)
184+
*codecs = &vcn_4_0_0_video_codecs_encode_vcn1;
185+
else
186+
*codecs = &vcn_4_0_0_video_codecs_decode_vcn1;
187+
} else {
188+
if (encode)
189+
*codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
190+
else
191+
*codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
192+
}
125193
}
126194
return 0;
127195
default:
@@ -730,8 +798,23 @@ static int soc21_common_late_init(void *handle)
730798
{
731799
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
732800

733-
if (amdgpu_sriov_vf(adev))
801+
if (amdgpu_sriov_vf(adev)) {
734802
xgpu_nv_mailbox_get_irq(adev);
803+
if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
804+
!amdgpu_sriov_is_av1_support(adev)) {
805+
amdgpu_virt_update_sriov_video_codec(adev,
806+
sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
807+
ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
808+
sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
809+
ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1));
810+
} else {
811+
amdgpu_virt_update_sriov_video_codec(adev,
812+
sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
813+
ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
814+
sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
815+
ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0));
816+
}
817+
}
735818

736819
return 0;
737820
}

‎drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1312,14 +1312,14 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep,
13121312
args->n_success = i+1;
13131313
}
13141314

1315-
mutex_unlock(&p->mutex);
1316-
13171315
err = amdgpu_amdkfd_gpuvm_sync_memory(dev->adev, (struct kgd_mem *) mem, true);
13181316
if (err) {
13191317
pr_debug("Sync memory failed, wait interrupted by user signal\n");
13201318
goto sync_memory_failed;
13211319
}
13221320

1321+
mutex_unlock(&p->mutex);
1322+
13231323
/* Flush TLBs after waiting for the page table updates to complete */
13241324
for (i = 0; i < args->n_devices; i++) {
13251325
peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
@@ -1335,9 +1335,9 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep,
13351335
bind_process_to_device_failed:
13361336
get_mem_obj_from_handle_failed:
13371337
map_memory_to_gpu_failed:
1338+
sync_memory_failed:
13381339
mutex_unlock(&p->mutex);
13391340
copy_from_user_failed:
1340-
sync_memory_failed:
13411341
kfree(devices_arr);
13421342

13431343
return err;
@@ -1351,6 +1351,7 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
13511351
void *mem;
13521352
long err = 0;
13531353
uint32_t *devices_arr = NULL, i;
1354+
bool flush_tlb;
13541355

13551356
if (!args->n_devices) {
13561357
pr_debug("Device IDs array empty\n");
@@ -1403,16 +1404,19 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
14031404
}
14041405
args->n_success = i+1;
14051406
}
1406-
mutex_unlock(&p->mutex);
14071407

1408-
if (kfd_flush_tlb_after_unmap(pdd->dev)) {
1408+
flush_tlb = kfd_flush_tlb_after_unmap(pdd->dev);
1409+
if (flush_tlb) {
14091410
err = amdgpu_amdkfd_gpuvm_sync_memory(pdd->dev->adev,
14101411
(struct kgd_mem *) mem, true);
14111412
if (err) {
14121413
pr_debug("Sync memory failed, wait interrupted by user signal\n");
14131414
goto sync_memory_failed;
14141415
}
1416+
}
1417+
mutex_unlock(&p->mutex);
14151418

1419+
if (flush_tlb) {
14161420
/* Flush TLBs after waiting for the page table updates to complete */
14171421
for (i = 0; i < args->n_devices; i++) {
14181422
peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
@@ -1428,9 +1432,9 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
14281432
bind_process_to_device_failed:
14291433
get_mem_obj_from_handle_failed:
14301434
unmap_memory_from_gpu_failed:
1435+
sync_memory_failed:
14311436
mutex_unlock(&p->mutex);
14321437
copy_from_user_failed:
1433-
sync_memory_failed:
14341438
kfree(devices_arr);
14351439
return err;
14361440
}

‎drivers/gpu/drm/amd/amdkfd/kfd_device.c

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,7 @@ static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
5959
unsigned int chunk_size);
6060
static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
6161

62+
static int kfd_resume_iommu(struct kfd_dev *kfd);
6263
static int kfd_resume(struct kfd_dev *kfd);
6364

6465
static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd)
@@ -624,7 +625,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
624625

625626
svm_migrate_init(kfd->adev);
626627

627-
if (kgd2kfd_resume_iommu(kfd))
628+
if (kfd_resume_iommu(kfd))
628629
goto device_iommu_error;
629630

630631
if (kfd_resume(kfd))
@@ -772,6 +773,14 @@ int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
772773
}
773774

774775
int kgd2kfd_resume_iommu(struct kfd_dev *kfd)
776+
{
777+
if (!kfd->init_complete)
778+
return 0;
779+
780+
return kfd_resume_iommu(kfd);
781+
}
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static int kfd_resume_iommu(struct kfd_dev *kfd)
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{
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int err = 0;
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