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ARM: dts: Fix wrong clocks for dra7 mcasp
The ahclkr clkctrl clock bit 28 only exists for mcasp 1 and 2 on dra7. This causes the following warning on beagle-x15: ti-sysc 48468000.target-module: could not add child clock ahclkr: -19 Also the mcasp clkctrl clock bits are wrong: For mcasp1 and 2 we have four clocks at bits 28, 24, 22 and 0: bit 28 is ahclkr bit 24 is ahclkx bit 22 is auxclk bit 0 is fck For mcasp3 to 8 we have three clocks at bits 24, 22 and 0. bit 24 is ahclkx bit 22 is auxclk bit 0 is fck We do not have currently mapped auxclk at bit 22 for the drivers, that can be added if needed. Fixes: 5241ccb ("ARM: dts: Add missing ranges for dra7 mcasp l3 ports") Cc: Suman Anna <[email protected]> Cc: Tero Kristo <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
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‎arch/arm/boot/dts/dra7-l4.dtsi

Lines changed: 21 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -2762,7 +2762,7 @@
27622762
interrupt-names = "tx", "rx";
27632763
dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
27642764
dma-names = "tx", "rx";
2765-
clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 22>,
2765+
clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
27662766
<&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
27672767
<&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
27682768
clock-names = "fck", "ahclkx", "ahclkr";
@@ -2799,8 +2799,8 @@
27992799
interrupt-names = "tx", "rx";
28002800
dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
28012801
dma-names = "tx", "rx";
2802-
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 22>,
2803-
<&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>,
2802+
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2803+
<&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
28042804
<&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
28052805
clock-names = "fck", "ahclkx", "ahclkr";
28062806
status = "disabled";
@@ -2818,9 +2818,8 @@
28182818
<SYSC_IDLE_SMART>;
28192819
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
28202820
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2821-
<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>,
2822-
<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 28>;
2823-
clock-names = "fck", "ahclkx", "ahclkr";
2821+
<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2822+
clock-names = "fck", "ahclkx";
28242823
#address-cells = <1>;
28252824
#size-cells = <1>;
28262825
ranges = <0x0 0x68000 0x2000>,
@@ -2836,7 +2835,7 @@
28362835
interrupt-names = "tx", "rx";
28372836
dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
28382837
dma-names = "tx", "rx";
2839-
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 22>,
2838+
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
28402839
<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
28412840
clock-names = "fck", "ahclkx";
28422841
status = "disabled";
@@ -2854,9 +2853,8 @@
28542853
<SYSC_IDLE_SMART>;
28552854
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
28562855
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2857-
<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>,
2858-
<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 28>;
2859-
clock-names = "fck", "ahclkx", "ahclkr";
2856+
<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2857+
clock-names = "fck", "ahclkx";
28602858
#address-cells = <1>;
28612859
#size-cells = <1>;
28622860
ranges = <0x0 0x6c000 0x2000>,
@@ -2872,7 +2870,7 @@
28722870
interrupt-names = "tx", "rx";
28732871
dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
28742872
dma-names = "tx", "rx";
2875-
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 22>,
2873+
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
28762874
<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
28772875
clock-names = "fck", "ahclkx";
28782876
status = "disabled";
@@ -2890,9 +2888,8 @@
28902888
<SYSC_IDLE_SMART>;
28912889
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
28922890
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2893-
<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>,
2894-
<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 28>;
2895-
clock-names = "fck", "ahclkx", "ahclkr";
2891+
<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2892+
clock-names = "fck", "ahclkx";
28962893
#address-cells = <1>;
28972894
#size-cells = <1>;
28982895
ranges = <0x0 0x70000 0x2000>,
@@ -2908,7 +2905,7 @@
29082905
interrupt-names = "tx", "rx";
29092906
dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
29102907
dma-names = "tx", "rx";
2911-
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 22>,
2908+
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
29122909
<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
29132910
clock-names = "fck", "ahclkx";
29142911
status = "disabled";
@@ -2926,9 +2923,8 @@
29262923
<SYSC_IDLE_SMART>;
29272924
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
29282925
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2929-
<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>,
2930-
<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 28>;
2931-
clock-names = "fck", "ahclkx", "ahclkr";
2926+
<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2927+
clock-names = "fck", "ahclkx";
29322928
#address-cells = <1>;
29332929
#size-cells = <1>;
29342930
ranges = <0x0 0x74000 0x2000>,
@@ -2944,7 +2940,7 @@
29442940
interrupt-names = "tx", "rx";
29452941
dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
29462942
dma-names = "tx", "rx";
2947-
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 22>,
2943+
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
29482944
<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
29492945
clock-names = "fck", "ahclkx";
29502946
status = "disabled";
@@ -2962,9 +2958,8 @@
29622958
<SYSC_IDLE_SMART>;
29632959
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
29642960
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2965-
<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>,
2966-
<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 28>;
2967-
clock-names = "fck", "ahclkx", "ahclkr";
2961+
<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2962+
clock-names = "fck", "ahclkx";
29682963
#address-cells = <1>;
29692964
#size-cells = <1>;
29702965
ranges = <0x0 0x78000 0x2000>,
@@ -2980,7 +2975,7 @@
29802975
interrupt-names = "tx", "rx";
29812976
dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
29822977
dma-names = "tx", "rx";
2983-
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 22>,
2978+
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
29842979
<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
29852980
clock-names = "fck", "ahclkx";
29862981
status = "disabled";
@@ -2998,9 +2993,8 @@
29982993
<SYSC_IDLE_SMART>;
29992994
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
30002995
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
3001-
<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>,
3002-
<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 28>;
3003-
clock-names = "fck", "ahclkx", "ahclkr";
2996+
<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
2997+
clock-names = "fck", "ahclkx";
30042998
#address-cells = <1>;
30052999
#size-cells = <1>;
30063000
ranges = <0x0 0x7c000 0x2000>,
@@ -3016,7 +3010,7 @@
30163010
interrupt-names = "tx", "rx";
30173011
dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
30183012
dma-names = "tx", "rx";
3019-
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 22>,
3013+
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
30203014
<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
30213015
clock-names = "fck", "ahclkx";
30223016
status = "disabled";

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