@@ -40,16 +40,11 @@ EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, SND_SOC_CS35L56_SHARED);
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static const struct reg_default cs35l56_reg_defaults [] = {
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/* no defaults for OTP_MEM - first read populates cache */
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- { CS35L56_ASP1_ENABLES1 , 0x00000000 },
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- { CS35L56_ASP1_CONTROL1 , 0x00000028 },
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- { CS35L56_ASP1_CONTROL2 , 0x18180200 },
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- { CS35L56_ASP1_CONTROL3 , 0x00000002 },
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- { CS35L56_ASP1_FRAME_CONTROL1 , 0x03020100 },
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- { CS35L56_ASP1_FRAME_CONTROL5 , 0x00020100 },
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- { CS35L56_ASP1_DATA_CONTROL1 , 0x00000018 },
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- { CS35L56_ASP1_DATA_CONTROL5 , 0x00000018 },
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-
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- /* no defaults for ASP1TX mixer */
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+ /*
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+ * No defaults for ASP1 control or ASP1TX mixer. See
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+ * cs35l56_populate_asp1_register_defaults() and
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+ * cs35l56_sync_asp1_mixer_widgets_with_firmware().
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+ */
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{ CS35L56_SWIRE_DP3_CH1_INPUT , 0x00000018 },
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{ CS35L56_SWIRE_DP3_CH2_INPUT , 0x00000019 },
@@ -210,26 +205,52 @@ static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg)
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}
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}
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+ static const struct reg_sequence cs35l56_asp1_defaults [] = {
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+ REG_SEQ0 (CS35L56_ASP1_ENABLES1 , 0x00000000 ),
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+ REG_SEQ0 (CS35L56_ASP1_CONTROL1 , 0x00000028 ),
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+ REG_SEQ0 (CS35L56_ASP1_CONTROL2 , 0x18180200 ),
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+ REG_SEQ0 (CS35L56_ASP1_CONTROL3 , 0x00000002 ),
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+ REG_SEQ0 (CS35L56_ASP1_FRAME_CONTROL1 , 0x03020100 ),
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+ REG_SEQ0 (CS35L56_ASP1_FRAME_CONTROL5 , 0x00020100 ),
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+ REG_SEQ0 (CS35L56_ASP1_DATA_CONTROL1 , 0x00000018 ),
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+ REG_SEQ0 (CS35L56_ASP1_DATA_CONTROL5 , 0x00000018 ),
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+ };
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+
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+ /*
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+ * The firmware can have control of the ASP so we don't provide regmap
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+ * with defaults for these registers, to prevent a regcache_sync() from
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+ * overwriting the firmware settings. But if the machine driver hooks up
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+ * the ASP it means the driver is taking control of the ASP, so then the
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+ * registers are populated with the defaults.
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+ */
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+ int cs35l56_init_asp1_regs_for_driver_control (struct cs35l56_base * cs35l56_base )
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+ {
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+ if (!cs35l56_base -> fw_owns_asp1 )
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+ return 0 ;
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+
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+ cs35l56_base -> fw_owns_asp1 = false;
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+
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+ return regmap_multi_reg_write (cs35l56_base -> regmap , cs35l56_asp1_defaults ,
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+ ARRAY_SIZE (cs35l56_asp1_defaults ));
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+ }
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+ EXPORT_SYMBOL_NS_GPL (cs35l56_init_asp1_regs_for_driver_control , SND_SOC_CS35L56_SHARED );
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+
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/*
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* The firmware boot sequence can overwrite the ASP1 config registers so that
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* they don't match regmap's view of their values. Rewrite the values from the
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* regmap cache into the hardware registers.
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*/
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int cs35l56_force_sync_asp1_registers_from_cache (struct cs35l56_base * cs35l56_base )
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{
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- struct reg_sequence asp1_regs [] = {
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- { .reg = CS35L56_ASP1_ENABLES1 },
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- { .reg = CS35L56_ASP1_CONTROL1 },
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- { .reg = CS35L56_ASP1_CONTROL2 },
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- { .reg = CS35L56_ASP1_CONTROL3 },
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- { .reg = CS35L56_ASP1_FRAME_CONTROL1 },
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- { .reg = CS35L56_ASP1_FRAME_CONTROL5 },
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- { .reg = CS35L56_ASP1_DATA_CONTROL1 },
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- { .reg = CS35L56_ASP1_DATA_CONTROL5 },
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- };
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+ struct reg_sequence asp1_regs [ARRAY_SIZE (cs35l56_asp1_defaults )];
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int i , ret ;
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- /* Read values from regmap cache into a write sequence */
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+ if (cs35l56_base -> fw_owns_asp1 )
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+ return 0 ;
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+
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+ memcpy (asp1_regs , cs35l56_asp1_defaults , sizeof (asp1_regs ));
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+
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+ /* Read current values from regmap cache into the write sequence */
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for (i = 0 ; i < ARRAY_SIZE (asp1_regs ); ++ i ) {
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ret = regmap_read (cs35l56_base -> regmap , asp1_regs [i ].reg , & asp1_regs [i ].def );
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if (ret )
@@ -307,10 +328,10 @@ int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base)
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reg = CS35L56_DSP1_HALO_STATE ;
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/*
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- * This can't be a regmap_read_poll_timeout() because cs35l56 will NAK
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- * I2C until it has booted which would terminate the poll
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+ * The regmap must remain in cache-only until the chip has
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+ * booted, so use a bypassed read of the status register.
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*/
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- poll_ret = read_poll_timeout (regmap_read , read_ret ,
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+ poll_ret = read_poll_timeout (regmap_read_bypassed , read_ret ,
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(val < 0xFFFF ) && (val >= CS35L56_HALO_STATE_BOOT_DONE ),
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CS35L56_HALO_STATE_POLL_US ,
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CS35L56_HALO_STATE_TIMEOUT_US ,
@@ -362,7 +383,8 @@ void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire)
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return ;
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cs35l56_wait_control_port_ready ();
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- regcache_cache_only (cs35l56_base -> regmap , false);
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+
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+ /* Leave in cache-only. This will be revoked when the chip has rebooted. */
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}
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EXPORT_SYMBOL_NS_GPL (cs35l56_system_reset , SND_SOC_CS35L56_SHARED );
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@@ -577,14 +599,14 @@ int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_sou
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cs35l56_issue_wake_event (cs35l56_base );
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out_sync :
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- regcache_cache_only (cs35l56_base -> regmap , false);
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-
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ret = cs35l56_wait_for_firmware_boot (cs35l56_base );
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if (ret ) {
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dev_err (cs35l56_base -> dev , "Hibernate wake failed: %d\n" , ret );
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goto err ;
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}
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+ regcache_cache_only (cs35l56_base -> regmap , false);
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+
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ret = cs35l56_mbox_send (cs35l56_base , CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE );
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if (ret )
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goto err ;
@@ -757,7 +779,7 @@ int cs35l56_hw_init(struct cs35l56_base *cs35l56_base)
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* devices so the REVID needs to be determined before waiting for the
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* firmware to boot.
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*/
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- ret = regmap_read (cs35l56_base -> regmap , CS35L56_REVID , & revid );
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+ ret = regmap_read_bypassed (cs35l56_base -> regmap , CS35L56_REVID , & revid );
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if (ret < 0 ) {
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dev_err (cs35l56_base -> dev , "Get Revision ID failed\n" );
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return ret ;
@@ -768,7 +790,7 @@ int cs35l56_hw_init(struct cs35l56_base *cs35l56_base)
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if (ret )
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return ret ;
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- ret = regmap_read (cs35l56_base -> regmap , CS35L56_DEVID , & devid );
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+ ret = regmap_read_bypassed (cs35l56_base -> regmap , CS35L56_DEVID , & devid );
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if (ret < 0 ) {
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dev_err (cs35l56_base -> dev , "Get Device ID failed\n" );
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return ret ;
@@ -787,6 +809,9 @@ int cs35l56_hw_init(struct cs35l56_base *cs35l56_base)
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cs35l56_base -> type = devid & 0xFF ;
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+ /* Silicon is now identified and booted so exit cache-only */
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+ regcache_cache_only (cs35l56_base -> regmap , false);
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+
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ret = regmap_read (cs35l56_base -> regmap , CS35L56_DSP_RESTRICT_STS1 , & secured );
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if (ret ) {
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dev_err (cs35l56_base -> dev , "Get Secure status failed\n" );
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