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Nikolaos Pasaloukosarndb
Nikolaos Pasaloukos
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arndb
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arm64: dts: Add initial support for Blaize BLZP1600 CB2
Add support for the Blaize CB2 development board based on the BLZP1600 SoC. This consists of a Carrier-Board-2 and a System-on-Module. Both BLZP1600 SoM and CB2 are available as products. CB2 (Pathfinder) has multiple peripherals like UART, I2C, SPI, GPIO, CSI (camera), DSI (display), USB-3.0 and Ethernet. Enable support for the Cryptocell, UART and I2C which are already fully supported by the drivers. The blaize-blzp1600.dtsi is the common part for the SoC, blaize-blzp1600-som.dtsi is the common part for the SoM and blaize-blzp1600-cb2.dts is the board specific file. Co-developed-by: James Cowgill <[email protected]> Signed-off-by: James Cowgill <[email protected]> Co-developed-by: Matt Redfearn <[email protected]> Signed-off-by: Matt Redfearn <[email protected]> Co-developed-by: Neil Jones <[email protected]> Signed-off-by: Neil Jones <[email protected]> Signed-off-by: Nikolaos Pasaloukos <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
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‎arch/arm64/boot/dts/Makefile

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@@ -10,6 +10,7 @@ subdir-y += apm
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subdir-y += apple
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subdir-y += arm
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subdir-y += bitmain
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subdir-y += blaize
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subdir-y += broadcom
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subdir-y += cavium
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subdir-y += exynos

‎arch/arm64/boot/dts/blaize/Makefile

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# SPDX-License-Identifier: GPL-2.0+
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dtb-$(CONFIG_ARCH_BLAIZE) += blaize-blzp1600-cb2.dtb

‎arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts

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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2024 Blaize, Inc. All rights reserved.
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*/
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/dts-v1/;
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#include "blaize-blzp1600-som.dtsi"
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/ {
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model = "Blaize BLZP1600 SoM1600P CB2 Development Board";
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compatible = "blaize,blzp1600-cb2", "blaize,blzp1600";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200";
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};
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};
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&i2c0 {
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clock-frequency = <100000>;
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status = "okay";
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};
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&i2c1 {
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clock-frequency = <100000>;
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status = "okay";
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};
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&i2c3 {
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clock-frequency = <100000>;
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status = "okay";
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gpio_expander: gpio@74 {
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compatible = "ti,tca9539";
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reg = <0x74>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-line-names = "RSP_PIN_7", /* GPIO_0 */
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"RSP_PIN_11", /* GPIO_1 */
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"RSP_PIN_13", /* GPIO_2 */
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"RSP_PIN_15", /* GPIO_3 */
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"RSP_PIN_27", /* GPIO_4 */
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"RSP_PIN_29", /* GPIO_5 */
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"RSP_PIN_31", /* GPIO_6 */
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"RSP_PIN_33", /* GPIO_7 */
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"RSP_PIN_37", /* GPIO_8 */
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"RSP_PIN_16", /* GPIO_9 */
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"RSP_PIN_18", /* GPIO_10 */
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"RSP_PIN_22", /* GPIO_11 */
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"RSP_PIN_28", /* GPIO_12 */
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"RSP_PIN_32", /* GPIO_13 */
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"RSP_PIN_36", /* GPIO_14 */
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"TP31"; /* GPIO_15 */
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};
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gpio_expander_m2: gpio@75 {
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compatible = "ti,tca9539";
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reg = <0x75>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-line-names = "M2_W_DIS1_N", /* GPIO_0 */
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"M2_W_DIS2_N", /* GPIO_1 */
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"M2_UART_WAKE_N", /* GPIO_2 */
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"M2_COEX3", /* GPIO_3 */
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"M2_COEX_RXD", /* GPIO_4 */
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"M2_COEX_TXD", /* GPIO_5 */
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"M2_VENDOR_PIN40", /* GPIO_6 */
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"M2_VENDOR_PIN42", /* GPIO_7 */
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"M2_VENDOR_PIN38", /* GPIO_8 */
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"M2_SDIO_RST_N", /* GPIO_9 */
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"M2_SDIO_WAKE_N", /* GPIO_10 */
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"M2_PETN1", /* GPIO_11 */
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"M2_PERP1", /* GPIO_12 */
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"M2_PERN1", /* GPIO_13 */
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"UIM_SWP", /* GPIO_14 */
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"UART1_TO_RSP"; /* GPIO_15 */
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};
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};

‎arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi

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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2024 Blaize, Inc. All rights reserved.
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*/
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#include "blaize-blzp1600.dtsi"
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/ {
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x1 0x0>;
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};
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};
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/* i2c4 bus is available only on the SoM, not on the board */
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&i2c4 {
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clock-frequency = <100000>;
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status = "okay";
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};
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&uart0 {
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status = "okay";
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};

‎arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi

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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2024 Blaize, Inc. All rights reserved.
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53";
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reg = <0x0 0x1>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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l2: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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};
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firmware {
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scmi {
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compatible = "arm,scmi-smc";
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arm,smc-id = <0x82002000>;
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#address-cells = <1>;
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#size-cells = <0>;
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shmem = <&scmi0_shm>;
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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scmi_rst: protocol@16 {
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reg = <0x16>;
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#reset-cells = <1>;
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};
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};
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* SCMI reserved buffer space on DDR space */
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scmi0_shm: scmi-shmem@800 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x800 0x0 0x80>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = /* Physical Secure PPI */
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<GIC_PPI 13 (GIC_CPU_MASK_RAW(0x3) |
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IRQ_TYPE_LEVEL_LOW)>,
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/* Physical Non-Secure PPI */
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<GIC_PPI 14 (GIC_CPU_MASK_RAW(0x3) |
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IRQ_TYPE_LEVEL_LOW)>,
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/* Hypervisor PPI */
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<GIC_PPI 10 (GIC_CPU_MASK_RAW(0x3) |
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IRQ_TYPE_LEVEL_LOW)>,
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/* Virtual PPI */
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<GIC_PPI 11 (GIC_CPU_MASK_RAW(0x3) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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soc@200000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x2 0x0 0x850000>;
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gic: interrupt-controller@410000 {
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compatible = "arm,gic-400";
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reg = <0x410000 0x20000>,
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<0x420000 0x20000>,
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<0x440000 0x20000>,
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<0x460000 0x20000>;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x3) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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uart0: serial@4d0000 {
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compatible = "ns16550a";
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reg = <0x4d0000 0x1000>;
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clocks = <&scmi_clk 59>;
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resets = <&scmi_rst 59>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart1: serial@4e0000 {
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compatible = "ns16550a";
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reg = <0x4e0000 0x1000>;
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clocks = <&scmi_clk 60>;
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resets = <&scmi_rst 60>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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i2c0: i2c@4f0000 {
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compatible = "snps,designware-i2c";
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reg = <0x4f0000 0x1000>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scmi_clk 54>;
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resets = <&scmi_rst 54>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@500000 {
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compatible = "snps,designware-i2c";
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reg = <0x500000 0x1000>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scmi_clk 55>;
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resets = <&scmi_rst 55>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@510000 {
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compatible = "snps,designware-i2c";
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reg = <0x510000 0x1000>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scmi_clk 56>;
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resets = <&scmi_rst 56>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c3: i2c@520000 {
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compatible = "snps,designware-i2c";
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reg = <0x520000 0x1000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scmi_clk 57>;
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resets = <&scmi_rst 57>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c4: i2c@530000 {
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compatible = "snps,designware-i2c";
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reg = <0x530000 0x1000>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scmi_clk 58>;
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resets = <&scmi_rst 58>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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arm_cc712: crypto@550000 {
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compatible = "arm,cryptocell-712-ree";
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reg = <0x550000 0x1000>;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scmi_clk 7>;
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};
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};
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};

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